74AUC16374 Series

16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

Catalog(2 parts)

Part	Input Capacitance▲▼	Output Type	Voltage - Supply▲▼	Voltage - Supply▲▼	Function	Mounting Type	Number of Bits per Element▲▼	Clock Frequency▲▼	Type	Package / Case	Number of Elements▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Max Propagation Delay @ V, Max CL▲▼	Current - Quiescent (Iq)▲▼	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Trigger Type	Supplier Device Package	Package / Case▲▼	Package / Case▲▼
Texas Instruments SN74AUC16374DGVR Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.173", 4.40mm Width)	2.9999999880125916e-12 F	Tri-State, Non-Inverted	0.800000011920929 V	2.700000047683716 V	Standard	Surface Mount	8 ul	250000000 Hz	D-Type	48-TFSOP	2 ul	85 °C	-40 °C	2.199999959984211e-9 s	0.000019999999494757503 A	0.008999999612569809 A	0.008999999612569809 A	Positive Edge
Texas Instruments SN74AUC16374DGGR Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)	2.9999999880125916e-12 F	Tri-State, Non-Inverted	0.800000011920929 V	2.700000047683716 V	Standard	Surface Mount	8 ul	250000000 Hz	D-Type	48-TFSOP	2 ul	85 °C	-40 °C	2.199999959984211e-9 s	0.000019999999494757503 A	0.008999999612569809 A	0.008999999612569809 A	Positive Edge	48-TSSOP	0.006099999882280827 m	0.006095999851822853 m

Key Features

• Member of the Texas Instruments Widebus™ FamilyOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 2.8 ns at 1.8 VLow Power Consumption, 20-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 2.8 ns at 1.8 VLow Power Consumption, 20-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.

Description

This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.