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74AS109 Series

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

Manufacturer: Texas Instruments

Catalog(7 parts)

PartNumber of Bits per Element▲▼Max Propagation Delay @ V, Max CL▲▼Voltage - Supply▲▼Voltage - Supply▲▼TypeFunctionMounting TypeTrigger TypeNumber of Elements▲▼Clock Frequency▲▼Operating Temperature▲▼Operating Temperature▲▼Current - Output High, Low▲▼Current - Output High, Low▲▼Supplier Device PackageOutput TypePackage / CasePackage / Case▲▼
Texas Instruments
SN74AS109ANSR
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.209", 5.30mm Width)
1 ul
8.999999856484921e-9 s
5.5 V
4.5 V
JK Type
Reset, Set(Preset)
Surface Mount
Positive Edge
2 ul
105000000 Hz
70 °C
0 °C
0.019999999552965164 A
0.0020000000949949026 A
16-SO
Complementary
16-SOIC (0.209", 5.30mm Width)
Texas Instruments
SN74AS109ANS
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.209", 5.30mm Width)
1 ul
8.999999856484921e-9 s
5.5 V
4.5 V
JK Type
Reset, Set(Preset)
Surface Mount
Positive Edge
2 ul
105000000 Hz
70 °C
0 °C
0.019999999552965164 A
0.0020000000949949026 A
16-SO
Complementary
16-SOIC (0.209", 5.30mm Width)
Texas Instruments
SN74AS109AD
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)
1 ul
8.999999856484921e-9 s
5.5 V
4.5 V
JK Type
Reset, Set(Preset)
Surface Mount
Positive Edge
2 ul
105000000 Hz
70 °C
0 °C
0.019999999552965164 A
0.0020000000949949026 A
16-SOIC
Complementary
16-SOIC
0.003911599982529879 m, 3.900000095367432 ul
Texas Instruments
SN74AS109N
Flip Flop Element Bit
Texas Instruments
SN74AS109ADRG4
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)
1 ul
8.999999856484921e-9 s
5.5 V
4.5 V
JK Type
Reset, Set(Preset)
Surface Mount
Positive Edge
2 ul
105000000 Hz
70 °C
0 °C
0.019999999552965164 A
0.0020000000949949026 A
16-SOIC
Complementary
16-SOIC
0.003911599982529879 m, 3.900000095367432 ul
Texas Instruments
SN74AS109ADR
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)
1 ul
8.999999856484921e-9 s
5.5 V
4.5 V
JK Type
Reset, Set(Preset)
Surface Mount
Positive Edge
2 ul
105000000 Hz
70 °C
0 °C
0.019999999552965164 A
0.0020000000949949026 A
16-SOIC
Complementary
16-SOIC
0.003911599982529879 m, 3.900000095367432 ul
Texas Instruments
SN74AS109AN
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-DIP (0.300", 7.62mm)
1 ul
8.999999856484921e-9 s
5.5 V
4.5 V
JK Type
Reset, Set(Preset)
Through Hole
Positive Edge
2 ul
105000000 Hz
70 °C
0 °C
0.019999999552965164 A
0.0020000000949949026 A
16-PDIP
Complementary
16-DIP
0.007619999814778566 m, 0.007619999814778566 m

Key Features

• Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPsPackage Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

Description

AI
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C. These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.