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CLVC2G74 Series

Automotive Catalog Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

Automotive Catalog Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

PartFunctionVoltage - Supply [Max]Voltage - Supply [Min]Number of Bits per ElementPackage / CasePackage / CasePackage / CaseCurrent - Output High, Low [custom]Current - Output High, Low [custom]QualificationGradeTypeMounting TypeOperating Temperature [Min]Operating Temperature [Max]Trigger TypeCurrent - Quiescent (Iq)Input CapacitanceClock FrequencyOutput TypeMax Propagation Delay @ V, Max CLNumber of Elements [custom]
Texas Instruments
CLVC2G74QDCURG4Q1
Reset, Set(Preset)
5.5 V
1.65 V
1
0.091 in
8-VFSOP
2.3 mm
24 mA
24 mA
AEC-Q100
Automotive
D-Type
Surface Mount
-40 °C
125 °C
Positive Edge
10 µA
5 pF
140 MHz
Complementary
5.1 ns
1

Key Features

Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 6.9 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 6.9 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

AI
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.