74ALVCH16721 Series

3.3-V 20-Bit Flip-Flop With 3-State Outputs

Catalog(3 parts)

Part	Number of Elements▲▼	Mounting Type	Supplier Device Package	Type	Package / Case▲▼	Package / Case▲▼	Package / Case	Voltage - Supply▲▼	Voltage - Supply▲▼	Trigger Type	Input Capacitance▲▼	Number of Bits per Element▲▼	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Max Propagation Delay @ V, Max CL▲▼	Clock Frequency▲▼	Function	Output Type	Operating Temperature▲▼	Operating Temperature▲▼
Texas Instruments SN74ALVCH16721DLR Flip Flop 1 Element D-Type 20 Bit Positive Edge 56-BSSOP (0.295", 7.50mm Width)	1 ul	Surface Mount	56-SSOP	D-Type	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	3.5999999046325684 V	1.649999976158142 V	Positive Edge	3.4999999860146898e-12 F	20 ul	0.024000000208616257 A	0.024000000208616257 A	4.2999999116943854e-9 s	150000000 Hz	Standard	Tri-State, Non-Inverted	85 °C	-40 °C
Texas Instruments SN74ALVCH16721DL Flip Flop 1 Element D-Type 20 Bit Positive Edge 56-BSSOP (0.295", 7.50mm Width)	1 ul	Surface Mount	56-SSOP	D-Type	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	3.5999999046325684 V	1.649999976158142 V	Positive Edge	3.4999999860146898e-12 F	20 ul	0.024000000208616257 A	0.024000000208616257 A	4.2999999116943854e-9 s	150000000 Hz	Standard	Tri-State, Non-Inverted	85 °C	-40 °C
Texas Instruments SN74ALVCH16721DGG Element Bit per Element Output

Key Features

• Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesWidebus, EPIC are trademarks of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesWidebus, EPIC are trademarks of Texas Instruments.

Description

This 20-bit flip-flop is designed specifically for 1.65-V to 3.6-V VCCoperation. The 20 flip-flops of the SN74ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored. A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16721 is characterized for operation from –40°C to 85°C. This 20-bit flip-flop is designed specifically for 1.65-V to 3.6-V VCCoperation. The 20 flip-flops of the SN74ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored. A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16721 is characterized for operation from –40°C to 85°C.