CDCDLP223 Series
3.3-V clock synthesizer for DLP systems
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
3.3-V clock synthesizer for DLP systems
| Part | Output | Differential - Input:Output | Number of Circuits | Input | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Frequency - Max [Max] | Type | Package / Case | Package / Case | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] | PLL | Supplier Device Package | Mounting Type | Divider/Multiplier [custom] | Divider/Multiplier [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCDLP223PW | LVTTL | No/Yes | 1 | Crystal | 1 | 3 | -40 °C | 85 °C | 400 MHz | Spread Spectrum Clock Driver | 0.173 in | 4.4 mm | 20-TSSOP | 3.6 V | 3 V | Yes with Bypass | 20-TSSOP | Surface Mount | ||
Texas Instruments CDCDLP223PWRG4 | LVTTL | No/Yes | 1 | Crystal | 1 | 3 | -40 °C | 85 °C | 400 MHz | Spread Spectrum Clock Driver | 0.173 in | 4.4 mm | 20-TSSOP | 3.6 V | 3 V | Yes with Bypass | 20-TSSOP | Surface Mount | ||
Texas Instruments CDCDLP223PWG4 | LVTTL | No/Yes | 1 | Crystal | 1 | 3 | -40 °C | 85 °C | 400 MHz | Spread Spectrum Clock Driver | 0.173 in | 4.4 mm | 20-TSSOP | 3.6 V | 3 V | Yes with Bypass | 20-TSSOP | Surface Mount |
Key Features
• High-Performance Clock SynthesizerUses a 20 MHz Crystal Input to Generate Multiple Output FrequenciesIntegrated Load Capacitance for 20 MHz Oscillator Reducing System CostAll PLL Loop Filter Components are IntegratedGenerates the Following Clocks:REF CLK 20 MHz (Buffered)XCG CLK 100 MHz With SSCDMD CLK 200-400 MHz With Selectable SSCVery Low Period Jitter Characteristic:±100 ps at 20 MHz Output±75 ps at 100 MHz and 200-400 MHz OutputsIncludes Spread-Spectrum Clocking (SSC), With Down Spread for 100 MHz and Center Spread for 200-400 MHzHCLK Differential Outputs for the 100 MHz and the 200-400 MHz ClockOperates From Single 3.3-V SupplyPackaged in TSSOP20Characterized for the Industrial Temperature Range -40°C to 85°CESD Protection Exceeds JESD222000-V Human-Body Model (A114-C) - MIL-STD-883, Method 3015TYPICAL APPLICATIONSCentral Clock Generator for DLP™ SystemsHigh-Performance Clock SynthesizerUses a 20 MHz Crystal Input to Generate Multiple Output FrequenciesIntegrated Load Capacitance for 20 MHz Oscillator Reducing System CostAll PLL Loop Filter Components are IntegratedGenerates the Following Clocks:REF CLK 20 MHz (Buffered)XCG CLK 100 MHz With SSCDMD CLK 200-400 MHz With Selectable SSCVery Low Period Jitter Characteristic:±100 ps at 20 MHz Output±75 ps at 100 MHz and 200-400 MHz OutputsIncludes Spread-Spectrum Clocking (SSC), With Down Spread for 100 MHz and Center Spread for 200-400 MHzHCLK Differential Outputs for the 100 MHz and the 200-400 MHz ClockOperates From Single 3.3-V SupplyPackaged in TSSOP20Characterized for the Industrial Temperature Range -40°C to 85°CESD Protection Exceeds JESD222000-V Human-Body Model (A114-C) - MIL-STD-883, Method 3015TYPICAL APPLICATIONSCentral Clock Generator for DLP™ Systems
Description
AI
The CDCDLP223 is a PLL-based high performance clock synthesizer that is optimized for use in DLP™ systems. It uses a 20 MHz crystal to generate the fundamental frequency and derives the frequencies for the 100 MHz HCLK and the 300 MHz HCLK output. Further, the CDCDLP223 generates a buffered copy of the 20 MHz Crystal Oscillator Frequency at the 20 MHz output terminal.
The 100 MHz HCLK output provides the reference clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which reduces Electro Magnetic Interference (EMI), is applied in the default configuration. The spread-spectrum clocking (SSC) is turned on and off via the serial control interface.
The 300 MHz HCLK output provides a 200-400 MHz clock signal for the DMD Control Logic of the DLP™ Control ASIC. Frequency selection in 20 MHz steps is possible via the serial control interface. Spread-spectrum clocking with ±1.0% or ±1.5% center spread is applied, which can be disabled via the serial control interface
The CDCDLP223 features a fail safe start-up circuit, which enables the PLLs only if a sufficient supply voltage is applied and a stable oscillation is delivered from the crystal oscillator. After the crystal start-up time and the PLL stabilization time, all outputs are ready for use.
The CDCDLP223 works from a single 3.3-V supply and is characterized for operation from -40°C to 85°C.
The CDCDLP223 is a PLL-based high performance clock synthesizer that is optimized for use in DLP™ systems. It uses a 20 MHz crystal to generate the fundamental frequency and derives the frequencies for the 100 MHz HCLK and the 300 MHz HCLK output. Further, the CDCDLP223 generates a buffered copy of the 20 MHz Crystal Oscillator Frequency at the 20 MHz output terminal.
The 100 MHz HCLK output provides the reference clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which reduces Electro Magnetic Interference (EMI), is applied in the default configuration. The spread-spectrum clocking (SSC) is turned on and off via the serial control interface.
The 300 MHz HCLK output provides a 200-400 MHz clock signal for the DMD Control Logic of the DLP™ Control ASIC. Frequency selection in 20 MHz steps is possible via the serial control interface. Spread-spectrum clocking with ±1.0% or ±1.5% center spread is applied, which can be disabled via the serial control interface
The CDCDLP223 features a fail safe start-up circuit, which enables the PLLs only if a sufficient supply voltage is applied and a stable oscillation is delivered from the crystal oscillator. After the crystal start-up time and the PLL stabilization time, all outputs are ready for use.
The CDCDLP223 works from a single 3.3-V supply and is characterized for operation from -40°C to 85°C.