Catalog(2 parts)
| Part | Mounting Type | Function | Applications | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Control Interface | Supplier Device Package | Package / Case |
|---|---|---|---|---|---|---|---|---|
Surface Mount | Digitizer | Consumer Video | 2 V, 3.5999999046325684 V | 1.7000000476837158 V, 1.7999999523162842 V, 3 V | I2C, Serial | 100-HTQFP (14x14) | 100-TQFP Exposed Pad | |
Surface Mount | Digitizer | Consumer Video | 2 V, 3.5999999046325684 V | 1.7000000476837158 V, 1.7999999523162842 V, 3 V | I2C, Serial | 100-HTQFP (14x14) | 100-TQFP Exposed Pad |
Key Features
• Analog Channels–6 dB to 6 dB Analog GainAnalog Input MUXsAuto Video ClampThree Digitizing Channels, Each With Independently Controllable Clamp, PGA, and ADCClamping: Selectable Clamping Between Bottom Level and Mid–levelOffset: 1024–Step Programmable RGB or YPbPr Offset ControlPGA: 8–Bit Programmable Gain AmplifierADC: 8/10–Bit 165/110 MSPS A/D ConverterAutomatic Level Control CircuitComposite Sync: Integrated Sync–on–Green Extraction From GreenLuminance ChannelSupport for DC and AC–Coupled Input SignalsPLLFully Integrated Analog PLL for Pixel Clock Generation12–165 MHz Pixel Clock Generation From HSYNC InputAdjustable PLL Loop Bandwidth for Minimum Jitter5–Bit Programmable Subpixel Accurate Positioning of Sampling PhaseOutput FormatterSupport for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board TracesDedicated DATACLK Output for Easy Latching of Output DataSystemIndustry–Standard Normal/Fast I2C Interface With Register Readback CapabilitySpace–Saving TQFP–100 Pin PackageThermally–Enhanced PowerPAD™ Package for Better Heat DissipationAPPLICATIONSLCD TV/Monitors/ProjectorsDLP TV/ProjectorsPDP TV/MonitorsPCTV Set–Top BoxesDigital Image ProcessingVideo Capture/Video EditingScan Rate/Image Resolution ConvertersVideo ConferencingVideo/Graphics Digitizing EquipmentAnalog Channels–6 dB to 6 dB Analog GainAnalog Input MUXsAuto Video ClampThree Digitizing Channels, Each With Independently Controllable Clamp, PGA, and ADCClamping: Selectable Clamping Between Bottom Level and Mid–levelOffset: 1024–Step Programmable RGB or YPbPr Offset ControlPGA: 8–Bit Programmable Gain AmplifierADC: 8/10–Bit 165/110 MSPS A/D ConverterAutomatic Level Control CircuitComposite Sync: Integrated Sync–on–Green Extraction From GreenLuminance ChannelSupport for DC and AC–Coupled Input SignalsPLLFully Integrated Analog PLL for Pixel Clock Generation12–165 MHz Pixel Clock Generation From HSYNC InputAdjustable PLL Loop Bandwidth for Minimum Jitter5–Bit Programmable Subpixel Accurate Positioning of Sampling PhaseOutput FormatterSupport for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board TracesDedicated DATACLK Output for Easy Latching of Output DataSystemIndustry–Standard Normal/Fast I2C Interface With Register Readback CapabilitySpace–Saving TQFP–100 Pin PackageThermally–Enhanced PowerPAD™ Package for Better Heat DissipationAPPLICATIONSLCD TV/Monitors/ProjectorsDLP TV/ProjectorsPDP TV/MonitorsPCTV Set–Top BoxesDigital Image ProcessingVideo Capture/Video EditingScan Rate/Image Resolution ConvertersVideo ConferencingVideo/Graphics Digitizing Equipment
Description
AI
TVP7001 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at 60 Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p. TVP7001 can be used to digitize CVBS and S–video signal with 10–bit ADCs.
The TVP7001 is powered from 3.3–V and 1.8–V supply and integrates a triple high–performance A/D converter with clamping functions and variable gain, independently programmable for each channel. The clamping timing window is provided by an external pulse or can be generated internally. The TVP7001 includes analog slicing circuitry on the Y or G input to support sync–on–luminance or sync–on–green extraction. In addition, TVP7001 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
TVP7001 also contains a complete analog PLL block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.
All programming of the part is done via an industry–standard I2C interface, which supports both reading and writing of register settings. The TVP7001 is available in a space–saving TQFP 100–pin PowerPAD package.
TVP7001 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at 60 Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p. TVP7001 can be used to digitize CVBS and S–video signal with 10–bit ADCs.
The TVP7001 is powered from 3.3–V and 1.8–V supply and integrates a triple high–performance A/D converter with clamping functions and variable gain, independently programmable for each channel. The clamping timing window is provided by an external pulse or can be generated internally. The TVP7001 includes analog slicing circuitry on the Y or G input to support sync–on–luminance or sync–on–green extraction. In addition, TVP7001 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
TVP7001 also contains a complete analog PLL block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.
All programming of the part is done via an industry–standard I2C interface, which supports both reading and writing of register settings. The TVP7001 is available in a space–saving TQFP 100–pin PowerPAD package.