74HCT174 Series

High Speed CMOS Logic Hex D-Type Flip-Flop with Reset

Catalog(4 parts)

Part	Output Type	Number of Elements▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Clock Frequency▲▼	Package / Case	Package / Case▲▼	Mounting Type	Max Propagation Delay @ V, Max CL▲▼	Number of Bits per Element▲▼	Type	Trigger Type	Current - Quiescent (Iq)▲▼	Input Capacitance▲▼	Current - Output High, Low▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Supplier Device Package
Texas Instruments CD74HCT174M96G4 Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	Non-Inverted	1 ul	-55 °C	125 °C	25000000 Hz	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Surface Mount	3.999999975690116e-8 s	6 ul	D-Type	Positive Edge	0.000007999999979801942 A	9.999999960041972e-12 F	0.004000000189989805 A, 0.004000000189989805 A	5.5 V	4.5 V	16-SOIC
Texas Instruments CD74HCT174M96 Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	Non-Inverted	1 ul	-55 °C	125 °C	25000000 Hz	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Surface Mount	3.999999975690116e-8 s	6 ul	D-Type	Positive Edge	0.000007999999979801942 A	9.999999960041972e-12 F	0.004000000189989805 A, 0.004000000189989805 A	5.5 V	4.5 V	16-SOIC
Texas Instruments CD74HCT174MT Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	Non-Inverted	1 ul	-55 °C	125 °C	25000000 Hz	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Surface Mount	3.999999975690116e-8 s	6 ul	D-Type	Positive Edge	0.000007999999979801942 A	9.999999960041972e-12 F	0.004000000189989805 A, 0.004000000189989805 A	5.5 V	4.5 V	16-SOIC
Texas Instruments CD74HCT174EG4 Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-DIP (0.300", 7.62mm)	Non-Inverted	1 ul	-55 °C	125 °C	25000000 Hz	16-DIP	0.007619999814778566 m, 0.007619999814778566 m	Through Hole	3.999999975690116e-8 s	6 ul	D-Type	Positive Edge	0.000007999999979801942 A	9.999999960041972e-12 F	0.004000000189989805 A, 0.004000000189989805 A	5.5 V	4.5 V	16-PDIP

Key Features

• Buffered Positive Edge Triggered ClockAsynchronous Common ResetFanout (Over Temperature Range)Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHBuffered Positive Edge Triggered ClockAsynchronous Common ResetFanout (Over Temperature Range)Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH

Description

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.