74AS174 Series

Hex D-Type Positive-Edge-Triggered Flip-Flops With Clear

Catalog(2 parts)

Part	Clock Frequency▲▼	Number of Elements▲▼	Mounting Type	Max Propagation Delay @ V, Max CL▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Type	Output Type	Number of Bits per Element▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Package / Case	Package / Case▲▼	Current - Quiescent (Iq)▲▼	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Supplier Device Package	Trigger Type
Texas Instruments SN74AS174DRG4 Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	100000000 Hz	1 ul	Surface Mount	9.99999993922529e-9 s	5.5 V	4.5 V	D-Type	Tri-State, Non-Inverted	6 ul	70 °C	0 °C	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	0.04500000178813934 A	0.019999999552965164 A	0.0020000000949949026 A	16-SOIC	Positive Edge
Texas Instruments SN74AS174D Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	100000000 Hz	1 ul	Surface Mount	9.99999993922529e-9 s	5.5 V	4.5 V	D-Type	Tri-State, Non-Inverted	6 ul	70 °C	0 °C	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	0.04500000178813934 A	0.019999999552965164 A	0.0020000000949949026 A	16-SOIC	Positive Edge

Key Features

• ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.