CDCE6214-Q1 Series
Ultra-low power clock generator supporting PCIe gen 1-5 with 2 inputs, 4 outputs and internal EEPROM
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Ultra-low power clock generator supporting PCIe gen 1-5 with 2 inputs, 4 outputs and internal EEPROM
| Part | Number of Circuits | Divider/Multiplier | Voltage - Supply [Max] | Voltage - Supply [Min] | Qualification | Package / Case | PLL | Input | Type | Frequency - Max [Max] | Mounting Type | Operating Temperature [Max] | Operating Temperature [Min] | Output | Supplier Device Package | Grade |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCE6214TWRGERQ1 | 1 | Yes/No | 3.465 V | 1.71 V | AEC-Q100 | 24-VFQFN Exposed Pad | Differential or Single-Ended | Clock Generator | 350 MHz | Surface Mount, Wettable Flank | 105 °C | -40 °C | HCSL, LVCMOS, LVDS | 24-VQFN (4x4) | Automotive | |
Texas Instruments CDCE6214TWRGETQ1 | 1 | Yes/No | 3.465 V | 1.71 V | AEC-Q100 | 24-VFQFN Exposed Pad | Differential or Single-Ended | Clock Generator | 350 MHz | Surface Mount, Wettable Flank | 105 °C | -40 °C | HCSL, LVCMOS, LVDS | 24-VQFN (4x4) | Automotive |
Key Features
• AEC-Q100 qualified for automotive applicationsTemperature grade 2: –40°C to +105°CFunctional Safety-CapableDocumentation available to aid functional safety system designConfigurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout> 100 MHz) as:Integer mode:Differential output: 350 fs typical, 600 fs maximumLVCMOS output: 1.05 ps typical, 1.5 ps maximumFractional mode:Differential output: 1.7 ps typical, 2.1 ps maximumLVCMOS output: 2.0 ps typical, 4.0 ps maximumSupports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC2.335-GHz to 2.625-GHz internal VCOTypical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.Universal clock input, two reference inputs for redundancyDifferential AC-coupled or LVCMOS: 10 MHz to 200 MHzCrystal: 10 MHz to 50 MHzFlexible output clock distribution4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHzCombination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pinsGlitchless output divider switching and output channel synchronizationIndividual output enable through GPIO and registerFrequency margining optionsDCO mode: frequency increment/decrement with 10ppb or less step-sizeFully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHzSingle or mixed supply for level translation: 1.8 V/2.5 V/3.3 VConfigurable GPIOs and flexible configuration optionsI2C-compatible interface: up to 400 kHzIntegrated EEPROM with two pages and external select pin. In-situ programming allowed.Supports 100-Ω systemsLow electromagnetic emissionsSmall footprint: 24-pin VQFN (4 mm × 4 mm)AEC-Q100 qualified for automotive applicationsTemperature grade 2: –40°C to +105°CFunctional Safety-CapableDocumentation available to aid functional safety system designConfigurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout> 100 MHz) as:Integer mode:Differential output: 350 fs typical, 600 fs maximumLVCMOS output: 1.05 ps typical, 1.5 ps maximumFractional mode:Differential output: 1.7 ps typical, 2.1 ps maximumLVCMOS output: 2.0 ps typical, 4.0 ps maximumSupports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC2.335-GHz to 2.625-GHz internal VCOTypical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.Universal clock input, two reference inputs for redundancyDifferential AC-coupled or LVCMOS: 10 MHz to 200 MHzCrystal: 10 MHz to 50 MHzFlexible output clock distribution4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHzCombination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pinsGlitchless output divider switching and output channel synchronizationIndividual output enable through GPIO and registerFrequency margining optionsDCO mode: frequency increment/decrement with 10ppb or less step-sizeFully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHzSingle or mixed supply for level translation: 1.8 V/2.5 V/3.3 VConfigurable GPIOs and flexible configuration optionsI2C-compatible interface: up to 400 kHzIntegrated EEPROM with two pages and external select pin. In-situ programming allowed.Supports 100-Ω systemsLow electromagnetic emissionsSmall footprint: 24-pin VQFN (4 mm × 4 mm)
Description
AI
The CDCE6214-Q1 is a four-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214-Q1 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.
The CDCE6214-Q1 is a four-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214-Q1 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.