74HCT646 Series
High Speed CMOS Logic Octal Bus Transceivers/Registers with 3-State Outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Octal Bus Transceivers/Registers with 3-State Outputs
| Part | Number of Bits per Element | Output Type | Package / Case [y] | Package / Case [x] | Package / Case | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] | Number of Elements [custom] | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Mounting Type | Voltage - Supply [Max] | Voltage - Supply [Min] | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HCT646M96 | 8 | 3-State | 7.5 mm | 0.295 in | 24-SOIC | 24-SOIC | -55 C | 125 °C | 1 | 6 mA | 6 mA | Surface Mount | 5.5 V | 4.5 V | |
Texas Instruments SN74HCT646DWR | 8 | 3-State | 7.5 mm | 0.295 in | 24-SOIC | 24-SOIC | -40 °C | 85 °C | 1 | 6 mA | 6 mA | Surface Mount | 5.5 V | 4.5 V | |
Texas Instruments SN74HCT646DW | 8 | 3-State | 7.5 mm | 0.295 in | 24-SOIC | 24-SOIC | -40 °C | 85 °C | 1 | 6 mA | 6 mA | Surface Mount | 5.5 V | 4.5 V | |
Texas Instruments SN74HCT646NT | 8 | 3-State | 24-DIP | 24-PDIP | -40 °C | 85 °C | 1 | 6 mA | 6 mA | Through Hole | 5.5 V | 4.5 V | 0.3 in, 7.62 mm |
Key Features
• 2-V to 6-V VCCOperation (CD54HC646)4.5-V to 5.5-V VCCOperation (CD74HCT646)Wide Operating Temperature Range of –55°C to 125°CBalanced Propagation Delays and Transition TimesStandard Outputs Drive Up To 15 LS-TTL LoadsSignificant Power Reduction Compared to LS-TTL Logic ICsInputs Are TTL-Voltage Compatible (CD74HCT646)Independent Registers for A and B BusesMultiplexed Real-Time and Stored DataTrue Data Paths2-V to 6-V VCCOperation (CD54HC646)4.5-V to 5.5-V VCCOperation (CD74HCT646)Wide Operating Temperature Range of –55°C to 125°CBalanced Propagation Delays and Transition TimesStandard Outputs Drive Up To 15 LS-TTL LoadsSignificant Power Reduction Compared to LS-TTL Logic ICsInputs Are TTL-Voltage Compatible (CD74HCT646)Independent Registers for A and B BusesMultiplexed Real-Time and Stored DataTrue Data Paths
Description
AI
The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.
Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.
Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.