74ACT11286 Series
9-Bit Parity Generators/Checkers With Bus Driver Parity I/O Ports
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Circuits | Operating Temperature▲▼ | Operating Temperature▲▼ | Mounting Type | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Logic Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
0.024000000208616257 A | 0.024000000208616257 A | 5.5 V | 4.5 V | 9-Bit | -40 °C | 85 °C | Surface Mount | 0.003899999894201755 m | 0.003911599982529879 m | 14-SOIC | Parity Generator/Checker | |
0.024000000208616257 A | 0.024000000208616257 A | 5.5 V | 4.5 V | 9-Bit | -40 °C | 85 °C | Through Hole | 0.007619999814778566 m | 0.007619999814778566 m | 14-DIP | Parity Generator/Checker |
Key Features
• Inputs Are TTL-Voltage CompatibleGenerates Either Odd or Even Parity for Nine Data LinesCascadable for n-Bits ParityCenter-Pin VCCand GND Configurations Minimize High-Speed Switching NoiseEPICTM(Enhanced-Performance Implanted CMOS) 1-m Process500-mA Typical Latch-Up Immunity at 125°CPackage Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)EPIC is a trademark of Texas Instruments Incorporated.Inputs Are TTL-Voltage CompatibleGenerates Either Odd or Even Parity for Nine Data LinesCascadable for n-Bits ParityCenter-Pin VCCand GND Configurations Minimize High-Speed Switching NoiseEPICTM(Enhanced-Performance Implanted CMOS) 1-m Process500-mA Typical Latch-Up Immunity at 125°CPackage Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)EPIC is a trademark of Texas Instruments Incorporated.
Description
AI
The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
Thecontrol input is implemented specifically to accommodate cascading. When theis low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.
The 74ACT11286 is characterized for operation from -40°C to 85°C.
The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
Thecontrol input is implemented specifically to accommodate cascading. When theis low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.
The 74ACT11286 is characterized for operation from -40°C to 85°C.