Catalog(2 parts)
| Part | Operating Temperature▲▼ | Operating Temperature▲▼ | Type | Qualification | Independent Circuits▲▼ | Voltage Supply Source | Mounting Type | Supplier Device Package | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Grade | Package / Case | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Circuit | Circuit▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
-55 °C | 125 °C | Decoder/Demultiplexer | MIL-PRF-38535L | 1 ul | Single Supply | Through Hole | 16-CDIP | 5.5 V | 4.5 V | Military | 16-CDIP (0.300", 7.62mm) | 0.004000000189989805 A | 0.0007999999797903001 A | 2:4 | 2 ul | |
Texas Instruments 5962-9750801QFA |
Key Features
• Applications:Dual 2-to 4-Line DecoderDual 1-to 4-Line Demultiplexer3-to 8-Line Decoder1-to 8-Line DemultiplexerIndividual Strobes Simplify Cascading for Decoding or Demultiplexing Larger WordsInput Clamping Diodes Simplify System DesignChoice of Outputs:Totem Pole ('155, 'LS155A)Open-Collector ('156, 'LS156)Applications:Dual 2-to 4-Line DecoderDual 1-to 4-Line Demultiplexer3-to 8-Line Decoder1-to 8-Line DemultiplexerIndividual Strobes Simplify Cascading for Decoding or Demultiplexing Larger WordsInput Clamping Diodes Simplify System DesignChoice of Outputs:Totem Pole ('155, 'LS155A)Open-Collector ('156, 'LS156)
Description
AI
These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.
These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.