74SSTVF16859 Series

500-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

Catalog(2 parts)

Part	Number of Bits▲▼	Supply Voltage▲▼	Supply Voltage▲▼	Package / Case▲▼	Package / Case	Package / Case▲▼	Mounting Type	Supplier Device Package	Logic Type	Operating Temperature▲▼	Operating Temperature▲▼	Supplier Device Package▲▼	Supplier Device Package▲▼
Texas Instruments SN74SSTVF16859GR Registered Buffer with SSTL_2 Compatible I/O for DDR IC 64-TSSOP	13 ul, 26 ul	2.700000047683716 V	2.299999952316284 V	0.006095999851822853 m	64-TFSOP	0.006099999882280827 m	Surface Mount	64-TSSOP	Registered Buffer with SSTL_2 Compatible I/O for DDR	70 °C	0 °C
Texas Instruments SN74SSTVF16859S8 Registered Buffer with SSTL_2 Compatible I/O for DDR IC 56-VQFN (8x8)	13 ul, 26 ul	2.700000047683716 V	2.299999952316284 V		56-VFQFN Exposed Pad		Surface Mount	56-VQFN	Registered Buffer with SSTL_2 Compatible I/O for DDR	70 °C	0 °C	8 ul	8 ul

Key Features

• Member of the Texas Instruments Widebus™ FamilyOperates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)Pinout and Functionality Compatible With JEDEC Standard SSTV16859600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications1-to-2 Outputs to Support Stacked DDR DIMMsOutput Edge-Control Circuitry Minimizes Switching Noise in an Unterminated LineOutputs Meet SSTL_2 Class I SpecificationsSupports SSTL_2 Data InputsDifferential Clock (CLK and CLK\) InputsSupports LVCMOS Switching Levels on the RESET\ InputRESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs LowPinout Optimizes DIMM PCB LayoutLatch-Up Performance Exceeds 100mA Per JESD 78, Class IIESD Protection Exceeds JESD222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyOperates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)Pinout and Functionality Compatible With JEDEC Standard SSTV16859600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications1-to-2 Outputs to Support Stacked DDR DIMMsOutput Edge-Control Circuitry Minimizes Switching Noise in an Unterminated LineOutputs Meet SSTL_2 Class I SpecificationsSupports SSTL_2 Data InputsDifferential Clock (CLK and CLK\) InputsSupports LVCMOS Switching Levels on the RESET\ InputRESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs LowPinout Optimizes DIMM PCB LayoutLatch-Up Performance Exceeds 100mA Per JESD 78, Class IIESD Protection Exceeds JESD222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.

Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCCoperation. All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads. The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low. The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up. This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCCoperation. All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads. The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low. The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.