74AUC1G74 Series
Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset
Manufacturer: Texas Instruments
Catalog(5 parts)
| Part | Current - Quiescent (Iq)▲▼ | Output Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Type | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Function | Mounting Type | Number of Elements▲▼ | Clock Frequency▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Number of Bits per Element▲▼ | Input Capacitance▲▼ | Trigger Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74AUC1G74DCURFlip Flop 1 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width) | 0.000009999999747378752 A | Complementary | 0.800000011920929 V | 2.700000047683716 V | D-Type | 0.008999999612569809 A | 0.008999999612569809 A | Reset, Set(Preset) | Surface Mount | 1 ul | 275000000 Hz | 1.8000000379103651e-9 s | 1 ul | 2.499999990010493e-12 F | Positive Edge | 85 °C | -40 °C | 0.002311399905011058 m | 8-VFSOP | 0.002300000051036477 m | |
Texas Instruments SN74AUC1G74DCTRFlip Flop 1 Element D-Type 1 Bit Positive Edge 8-LSSOP, 8-MSOP (0.110", 2.80mm Width) | 0.000009999999747378752 A | Complementary | 0.800000011920929 V | 2.700000047683716 V | D-Type | 0.008999999612569809 A | 0.008999999612569809 A | Reset, Set(Preset) | Surface Mount | 1 ul | 275000000 Hz | 1.8000000379103651e-9 s | 1 ul | 2.499999990010493e-12 F | Positive Edge | 85 °C | -40 °C | SM8 | |||
0.000009999999747378752 A | Complementary | 0.800000011920929 V | 2.700000047683716 V | D-Type | 0.008999999612569809 A | 0.008999999612569809 A | Reset, Set(Preset) | Surface Mount | 1 ul | 275000000 Hz | 1.8000000379103651e-9 s | 1 ul | 2.499999990010493e-12 F | Positive Edge | 85 °C | -40 °C | 8-XFBGA, DSBGA | 8-DSBGA | |||
Texas Instruments SN74AUC1G74DCURG4Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width) | 0.000009999999747378752 A | Complementary | 0.800000011920929 V | 2.700000047683716 V | D-Type | 0.008999999612569809 A | 0.008999999612569809 A | Reset, Set(Preset) | Surface Mount | 1 ul | 275000000 Hz | 1.8000000379103651e-9 s | 1 ul | 2.499999990010493e-12 F | Positive Edge | 85 °C | -40 °C | 0.002311399905011058 m | 8-VFSOP | 0.002300000051036477 m |
Key Features
• Available in the Texas Instruments NanoFree™ PackageOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 1.5 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)NanoFree Is a trademark of Texas InstrumentsAvailable in the Texas Instruments NanoFree™ PackageOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 1.5 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)NanoFree Is a trademark of Texas Instruments
Description
AI
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, theCLRinput overrides thePREinput when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, theCLRinput overrides thePREinput when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.