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SM320F2812-EP Series

C2000™ Enhanced Product 32-bit MCU with 150 MHz, 256 KB Flash, EMIF

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

C2000™ Enhanced Product 32-bit MCU with 150 MHz, 256 KB Flash, EMIF

PartCore SizePackage / CaseSupplier Device PackageRAM SizeData ConvertersVoltage - Supply (Vcc/Vdd) [Min]Voltage - Supply (Vcc/Vdd) [Max]Operating Temperature [Min]Operating Temperature [Max]Program Memory TypeMounting TypeSpeedOscillator TypeNumber of I/OCore ProcessorProgram Memory SizePeripheralsInterfaceVoltage - I/ONon-Volatile MemoryNon-Volatile MemoryClock RateVoltage - CoreOn-Chip RAMType
Texas Instruments
SM320F2812PGFMEPG4
32-Bit Single-Core
176-LQFP
176-LQFP (24x24)
18 K
12 b, 16
1.81 V
2 V
-55 C
125 °C
FLASH
Surface Mount
150 MHz
Internal
56
C28x
256 KB
DMA, POR, PWM, WDT
Texas Instruments
V62/05601-03ZE
176-LQFP
176-LQFP (24x24)
-55 C
125 °C
Surface Mount
CAN, McBSP, SCI, SPI, UART
3.3 V
FLASH
256 MB
135 MHz, 150 MHz
1.8 V, 1.9 V
36 kB
Fixed Point
Texas Instruments
SM320F2812PGFMEP
32-Bit Single-Core
176-LQFP
176-LQFP (24x24)
18 K
12 b, 16
1.81 V
2 V
-55 C
125 °C
FLASH
Surface Mount
150 MHz
Internal
56
C28x
256 KB
DMA, POR, PWM, WDT

Key Features

Controlled BaselineOne Assembly/Test/Fabrication SiteExtended Temperature Performance of –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)High-Performance Static CMOS Technology150 MHz (6.67-ns Cycle Time)Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) DesignJTAG Boundary Scan Support(2)High-Performance 32-Bit CPU (320C28x)16 × 16 and 32 × 32 MAC Operations16 × 16 Dual MACHarvard Bus ArchitectureAtomic OperationsFast Interrupt Response and ProcessingUnified Memory Programming Model4M Linear Program/Data Address ReachCode-Efficient (in C/C++ and Assembly)320F24x/LF240x Processor Source Code CompatibleOn-Chip MemoryFlash Devices: Up to 128K × 16 Flash(Four 8K × 16 and Six 16K × 16 Sectors)ROM Devices: Up to 128K × 16 ROM1K × 16 OTP ROML0 and L1: 2 Blocks of 4K × 16 Each Single-Access RAM (SARAM)H0: 1 Block of 8K × 16 SARAMM0 and M1: 2 Blocks of 1K × 16 Each SARAMBoot ROM (4K × 16)With Software Boot ModesStandard Math TablesExternal Interface (2812)Over 1M × 16 Total MemoryProgrammable Wait StatesProgrammable Read/Write Strobe TimingThree Individual Chip SelectsClock and System ControlDynamic PLL Ratio Changes SupportedOn-Chip OscillatorWatchdog Timer ModuleThree External InterruptsPeripheral Interrupt Expansion (PIE) BlockThat Supports 45 Peripheral InterruptsThree 32-Bit CPU-Timers128-Bit Security Key/LockProtects Flash/ROM/OTP and L0/L1 SARAMPrevents Firmware Reverse EngineeringMotor Control PeripheralsTwo Event Managers (EVA, EVB)Compatible to 240xA DevicesSerial Port PeripheralsSerial Peripheral Interface (SPI)Two Serial Communications Interfaces (SCIs), Standard UARTEnhanced Controller Area Network (eCAN)Multichannel Buffered Serial Port (McBSP)12-Bit ADC, 16 Channels2 × 8 Channel Input MultiplexerTwo Sample-and-HoldSingle/Simultaneous ConversionsFast Conversion Rate: 80 ns/12.5 MSPSUp to 56 General Purpose I/O (GPIO) PinsAdvanced Emulation FeaturesAnalysis and Breakpoint FunctionsReal-Time Debug via HardwareDevelopment Tools IncludeANSI C/C++ Compiler/Assembler/LinkerCode Composer Studio™ IDEDSP/BIOS™Low-Power Modes and Power SavingsIDLE, STANDBY, HALT Modes SupportedDisable Individual Peripheral ClocksPackage Options179-Ball MicroStar BGA™ (GHH), (2812)176-Pin Low-Profile Quad Flatpack (LQFP) (PGF) (2812)TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.(2)IEEE Standard 1149.1-1990, IEEE Standard Test-Access PortControlled BaselineOne Assembly/Test/Fabrication SiteExtended Temperature Performance of –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)High-Performance Static CMOS Technology150 MHz (6.67-ns Cycle Time)Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) DesignJTAG Boundary Scan Support(2)High-Performance 32-Bit CPU (320C28x)16 × 16 and 32 × 32 MAC Operations16 × 16 Dual MACHarvard Bus ArchitectureAtomic OperationsFast Interrupt Response and ProcessingUnified Memory Programming Model4M Linear Program/Data Address ReachCode-Efficient (in C/C++ and Assembly)320F24x/LF240x Processor Source Code CompatibleOn-Chip MemoryFlash Devices: Up to 128K × 16 Flash(Four 8K × 16 and Six 16K × 16 Sectors)ROM Devices: Up to 128K × 16 ROM1K × 16 OTP ROML0 and L1: 2 Blocks of 4K × 16 Each Single-Access RAM (SARAM)H0: 1 Block of 8K × 16 SARAMM0 and M1: 2 Blocks of 1K × 16 Each SARAMBoot ROM (4K × 16)With Software Boot ModesStandard Math TablesExternal Interface (2812)Over 1M × 16 Total MemoryProgrammable Wait StatesProgrammable Read/Write Strobe TimingThree Individual Chip SelectsClock and System ControlDynamic PLL Ratio Changes SupportedOn-Chip OscillatorWatchdog Timer ModuleThree External InterruptsPeripheral Interrupt Expansion (PIE) BlockThat Supports 45 Peripheral InterruptsThree 32-Bit CPU-Timers128-Bit Security Key/LockProtects Flash/ROM/OTP and L0/L1 SARAMPrevents Firmware Reverse EngineeringMotor Control PeripheralsTwo Event Managers (EVA, EVB)Compatible to 240xA DevicesSerial Port PeripheralsSerial Peripheral Interface (SPI)Two Serial Communications Interfaces (SCIs), Standard UARTEnhanced Controller Area Network (eCAN)Multichannel Buffered Serial Port (McBSP)12-Bit ADC, 16 Channels2 × 8 Channel Input MultiplexerTwo Sample-and-HoldSingle/Simultaneous ConversionsFast Conversion Rate: 80 ns/12.5 MSPSUp to 56 General Purpose I/O (GPIO) PinsAdvanced Emulation FeaturesAnalysis and Breakpoint FunctionsReal-Time Debug via HardwareDevelopment Tools IncludeANSI C/C++ Compiler/Assembler/LinkerCode Composer Studio™ IDEDSP/BIOS™Low-Power Modes and Power SavingsIDLE, STANDBY, HALT Modes SupportedDisable Individual Peripheral ClocksPackage Options179-Ball MicroStar BGA™ (GHH), (2812)176-Pin Low-Profile Quad Flatpack (LQFP) (PGF) (2812)TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.(2)IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port

Description

AI
The SM320F2810-EP, SM320F2811-EP, SM320F2812-EP, SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview. Throughout this document, SM320F2810-EP, SM320F2811-EP, and SM320F2812-EP are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and 2812 denotes both F2812 and C2812 devices. The SM320F2810-EP, SM320F2811-EP, SM320F2812-EP, SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview. Throughout this document, SM320F2810-EP, SM320F2811-EP, and SM320F2812-EP are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and 2812 denotes both F2812 and C2812 devices.