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74LVC574 Series

Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs

Manufacturer: Texas Instruments

Catalog(14 parts)

PartNumber of Bits per Element▲▼Mounting TypeCurrent - Output High, Low▲▼Current - Output High, Low▲▼Input Capacitance▲▼Trigger TypeVoltage - Supply▲▼Voltage - Supply▲▼Current - Quiescent (Iq)▲▼Operating Temperature▲▼Operating Temperature▲▼Number of Elements▲▼Output TypePackage / CasePackage / Case▲▼Package / Case▲▼FunctionTypeSupplier Device PackageClock Frequency▲▼Max Propagation Delay @ V, Max CL▲▼Package / Case▲▼GradeQualification
Texas Instruments
SN74LVC574AN
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-DIP (0.300", 7.62mm)
8 ul
Through Hole
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-DIP
0.007619999814778566 m
0.007619999814778566 m
Standard
D-Type
20-PDIP
150000000 Hz
6.800000118545313e-9 s
Texas Instruments
SN74LVC574AQPWREP
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
2 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-TSSOP
0.004399999976158142 m
Standard
D-Type
20-TSSOP
150000000 Hz
7.000000135093387e-9 s
0.004394200164824724 m
Texas Instruments
SN74LVC574APWR
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-TSSOP
0.004399999976158142 m
Standard
D-Type
20-TSSOP
150000000 Hz
6.800000118545313e-9 s
0.004394200164824724 m
Texas Instruments
SN74LVC574ADW
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-SOIC
Standard
D-Type
20-SOIC
150000000 Hz
6.800000118545313e-9 s
0.007493000011891127 m, 0.007499999832361937 m
Texas Instruments
SN74LVC574AZQNR
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-VFBGA
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000001500000053056283 A
-40 °C
85 °C
1 ul
Tri-State, Non-Inverted
20-VFBGA
Standard
D-Type
20-BGA MICROSTAR JUNIOR (4x3)
150000000 Hz
6.800000118545313e-9 s
Texas Instruments
SN74LVC574APWT
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-TSSOP
0.004399999976158142 m
Standard
D-Type
20-TSSOP
150000000 Hz
6.800000118545313e-9 s
0.004394200164824724 m
Texas Instruments
SN74LVC574ADWRE4
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-SOIC
Standard
D-Type
20-SOIC
150000000 Hz
6.800000118545313e-9 s
0.007493000011891127 m, 0.007499999832361937 m
Texas Instruments
SN74LVC574ADWR
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000001500000053056283 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-SOIC
Standard
D-Type
20-SOIC
150000000 Hz
6.800000118545313e-9 s
0.007493000011891127 m, 0.007499999832361937 m
Texas Instruments
SN74LVC574APWRG4
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-TSSOP
0.004399999976158142 m
Standard
D-Type
20-TSSOP
150000000 Hz
6.800000118545313e-9 s
0.004394200164824724 m
Texas Instruments
SN74LVC574AQPWRQ1
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
2 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-TSSOP
0.004399999976158142 m
Standard
D-Type
20-TSSOP
150000000 Hz
7.000000135093387e-9 s
0.004394200164824724 m
Automotive
AEC-Q100
Texas Instruments
SN74LVC574ADBR
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SSOP (0.209", 5.30mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-SSOP
Standard
D-Type
20-SSOP
150000000 Hz
6.800000118545313e-9 s
0.0052999998442828655 m, 0.005308600142598152 m
Texas Instruments
SN74LVC574ADGVR
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TFSOP (0.173", 4.40mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-TFSOP
0.004394200164824724 m
0.004399999976158142 m
Standard
D-Type
20-TVSOP
150000000 Hz
6.800000118545313e-9 s
Texas Instruments
SN74LVC574ARGYR
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-VFQFN Exposed Pad
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000001500000053056283 A
-40 °C
85 °C
1 ul
Tri-State, Non-Inverted
20-VFQFN Exposed Pad
Standard
D-Type
20-VQFN (3.5x4.5)
150000000 Hz
6.800000118545313e-9 s
Texas Instruments
SN74LVC574ANS
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.209", 5.30mm Width)
8 ul
Surface Mount
0.024000000208616257 A
0.024000000208616257 A
3.999999984016789e-12 F
Positive Edge
3.5999999046325684 V
1.649999976158142 V
0.000009999999747378752 A
-40 °C
125 °C
1 ul
Tri-State, Non-Inverted
20-SOIC
Standard
D-Type
20-SO
150000000 Hz
6.800000118545313e-9 s
0.0052999998442828655 m, 0.005308600142598152 m

Key Features

• Operate From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VSpecified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°CMax tpdof 7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupport Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Operate From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VSpecified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°CMax tpdof 7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupport Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

AI
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.