SN74AUC1G80 Series

Single Positive-Edge-Triggered D-Type Flip-Flop

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop

Part	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Input Capacitance	Package / Case	Max Propagation Delay @ V, Max CL [Max]	Trigger Type	Clock Frequency	Current - Quiescent (Iq)	Function	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Type	Number of Bits per Element	Supplier Device Package [x]	Supplier Device Package [y]
Texas Instruments SN74AUC1G80DBVR	85 °C	-40 °C	1	Surface Mount	9 mA	9 mA	1.81 mOhm	2.5 pF	SC-74A SOT-753	1.8 ns	Positive Edge	275 MHz	10 µA	Standard	2.7 V	0.8 V	SOT-23-5	D-Type	1
Texas Instruments SN74AUC1G80DCKRG4	85 °C	-40 °C	1	Surface Mount	9 mA	9 mA	1.81 mOhm	2.5 pF	5-TSSOP SC-70-5 SOT-353	1.8 ns	Positive Edge	275 MHz	10 µA	Standard	2.7 V	0.8 V	SC-70-5	D-Type	1
Texas Instruments SN74AUC1G80YEPR	85 °C	-40 °C	1	Surface Mount	9 mA	9 mA	1.81 mOhm	2.5 pF	5-XFBGA DSBGA	1.8 ns	Positive Edge	275 MHz	10 µA	Standard	2.7 V	0.8 V	5-DSBGA	D-Type	1	1.4	0.9
Texas Instruments SN74AUC1G80DCKR	85 °C	-40 °C	1	Surface Mount	9 mA	9 mA	1.81 mOhm	2.5 pF	5-TSSOP SC-70-5 SOT-353	1.8 ns	Positive Edge	275 MHz	10 µA	Standard	2.7 V	0.8 V	SC-70-5	D-Type	1
Texas Instruments SN74AUC1G80YEAR	85 °C	-40 °C	1	Surface Mount	9 mA	9 mA	1.81 mOhm	2.5 pF	5-XFBGA DSBGA	1.8 ns	Positive Edge	275 MHz	10 µA	Standard	2.7 V	0.8 V	5-DSBGA	D-Type	1	1.4	0.9

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop

Key Features

• Available in the Texas Instruments NanoFree™ PackageOptimized for 1.8-V Operation and Is 3.6-VI/O Tolerant to Support Mixed-Mode SignalOperationIoffSupports Partial-Power-Down ModeOperationSub-1-V OperableMax tpdof 1.9 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)NanoFree is a trademark of Texas Instruments.Available in the Texas Instruments NanoFree™ PackageOptimized for 1.8-V Operation and Is 3.6-VI/O Tolerant to Support Mixed-Mode SignalOperationIoffSupports Partial-Power-Down ModeOperationSub-1-V OperableMax tpdof 1.9 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)NanoFree is a trademark of Texas Instruments.

Description

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.