CDCLVP2108 Series

Low jitter, dual 1:8 universal-to-LVPECL buffer

Link to Manufacturer Page: https://www.ti.com/

Catalog

Low jitter, dual 1:8 universal-to-LVPECL buffer

Part	Output	Input	Package / Case	Voltage - Supply [Min]	Voltage - Supply [Max]	Type	Mounting Type	Ratio - Input:Output [custom]	Supplier Device Package	Number of Circuits	Frequency - Max [Max]	Operating Temperature [Min]	Operating Temperature [Max]	Utilized IC / Part	Supplied Contents	Function
Texas Instruments CDCLVP2108RGZT	LVPECL	LVCMOS, LVDS, LVPECL, LVTTL	48-VFQFN Exposed Pad	2.375 V	3.6 V	Fanout Buffer (Distribution)	Surface Mount	1:16	48-VQFN (7x7)	2	2 GHz	-40 °C	85 °C
Texas Instruments CDCLVP2108EVM						Timing								CDCLVP2108	Board(s)	Clock Buffer
Texas Instruments CDCLVP2108RGZR	LVPECL	LVCMOS, LVDS, LVPECL, LVTTL	48-VFQFN Exposed Pad	2.375 V	3.6 V	Fanout Buffer (Distribution)	Surface Mount	1:16	48-VQFN (7x7)	2	2 GHz	-40 °C	85 °C

Key Features

• Dual 1:8 Differential BufferTwo Clock InputsUniversal Inputs Can Accept LVPECL, LVDS,LVCMOS/LVTTL16 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 115 mAVery Low Additive Jitter: <100 fs, RMSin 10-kHz to 20-MHz Offset Range2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Within Bank Output Skew: 25 psLVPECL Reference Voltage, VAC_REF,Available for Capacitive-Coupled InputsIndustrial Temperature Range: –l40°Cto +85°CSupports 105°C PCB Temperature (Measuredwith a Thermal Pad)Available in 7-mm × 7-mm, 48-Pin VQFN(RGZ) PackageESD Protection Exceeds 2000 V (HBM)Dual 1:8 Differential BufferTwo Clock InputsUniversal Inputs Can Accept LVPECL, LVDS,LVCMOS/LVTTL16 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 115 mAVery Low Additive Jitter: <100 fs, RMSin 10-kHz to 20-MHz Offset Range2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Within Bank Output Skew: 25 psLVPECL Reference Voltage, VAC_REF,Available for Capacitive-Coupled InputsIndustrial Temperature Range: –l40°Cto +85°CSupports 105°C PCB Temperature (Measuredwith a Thermal Pad)Available in 7-mm × 7-mm, 48-Pin VQFN(RGZ) PackageESD Protection Exceeds 2000 V (HBM)

Description

The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications. The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a 7-mm × 7-mm, VQFN-48 package. The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications. The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a 7-mm × 7-mm, VQFN-48 package.