74ALS174 Series

Hex D-Type Positive-Edge-Triggered Flip-Flops With Clear

Catalog(4 parts)

Part	Max Propagation Delay @ V, Max CL▲▼	Current - Quiescent (Iq)▲▼	Number of Elements▲▼	Trigger Type	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Mounting Type	Type	Operating Temperature▲▼	Package / Case▲▼	Package / Case	Output Type	Supplier Device Package	Clock Frequency▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Number of Bits per Element▲▼
Texas Instruments SN74ALS174N Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-DIP (0.300", 7.62mm)	1.6999999630229468e-8 s	0.01899999938905239 A	1 ul	Positive Edge	0.00800000037997961 A	0.00039999998989515007 A	Through Hole	D-Type	70 °C	0.007619999814778566 m, 0.007619999814778566 m	16-DIP	Non-Inverted	16-PDIP	50000000 Hz	5.5 V	4.5 V	6 ul
Texas Instruments SN74ALS174NSR Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.209", 5.30mm Width)	1.6999999630229468e-8 s	0.01899999938905239 A	1 ul	Positive Edge	0.00800000037997961 A	0.00039999998989515007 A	Surface Mount	D-Type	70 °C		16-SOIC (0.209", 5.30mm Width)	Non-Inverted	16-SO	50000000 Hz	5.5 V	4.5 V	6 ul
Texas Instruments SN74ALS174DR Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	1.6999999630229468e-8 s	0.01899999938905239 A	1 ul	Positive Edge	0.00800000037997961 A	0.00039999998989515007 A	Surface Mount	D-Type	70 °C	0.003911599982529879 m, 3.900000095367432 ul	16-SOIC	Non-Inverted	16-SOIC	50000000 Hz	5.5 V	4.5 V	6 ul
Texas Instruments SN74ALS174D Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	1.6999999630229468e-8 s	0.01899999938905239 A	1 ul	Positive Edge	0.00800000037997961 A	0.00039999998989515007 A	Surface Mount	D-Type	70 °C	0.003911599982529879 m, 3.900000095367432 ul	16-SOIC	Non-Inverted	16-SOIC	50000000 Hz	5.5 V	4.5 V	6 ul

Key Features

• ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.