SN74LVTH16373-EP Series

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs

Catalog

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs

Part	Package Name	Package Length	Package Width	Current - Output High	Current - Output Low	Circuit	Output Type	Mounting Type	Delay Time - Propagation	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Operating Temperature (Min)	Operating Temperature (Max)	Independent Circuits	Logic Type
Texas Instruments CLVTH16373IDGGREP	48-TFSOP 48-TSSOP	0.24 in	6.1 mm	32 mA	64 mA	8:8	Tri-State	Surface Mount	2.9 ns	3.6 V	2.7 V	-40 °C	85 °C	2	D-Type Transparent Latch
Texas Instruments V62/04712-01XE	48-TFSOP 48-TSSOP	0.24 in	6.1 mm	32 mA	64 mA	8:8	Non-Inverted Tri-State	Surface Mount	3 ns	3.6 V	2.7 V	-40 °C	85 °C	2	D-Type Transparent Latch
Texas Instruments CLVTH16373IDLREP	48-BSSOP 48-SSOP	0.295 in	7.5 mm	32 mA	64 mA	8:8	Tri-State	Surface Mount	2.9 ns	3.6 V	2.7 V	-40 °C	85 °C	2	D-Type Transparent Latch

Catalog

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs

Description

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.