74LS112 Series

Catalog

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Part	Output Type	Number of Bits per Element	Current - Output High	Current - Output Low	Trigger Type	Clock Frequency	Package Name	Function	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Type	Max Propagation Delay	Max CL	Package Width	Package Length	Mounting Type	Operating Temperature (Max)	Current - Quiescent (Iq)	Number of Elements
Texas Instruments SN74LS112ADR	Complementary	1 bits	400 µA	8 mA	Negative Edge	45 MHz	16-SOIC	Set(Preset) and Reset	5.25 V	4.75 V	JK Type	20 ns	15 pF	3.9 mm	0.154 in	Surface Mount	70 °C	6 mA	2
Texas Instruments SN74LS112ADRE4	Complementary	1 bits	400 µA	8 mA	Negative Edge	45 MHz	16-SOIC	Set(Preset) and Reset	5.25 V	4.75 V	JK Type	20 ns	15 pF	3.9 mm	0.154 in	Surface Mount	70 °C	6 mA	2
Texas Instruments SN74LS112ANSR	Complementary	1 bits	400 µA	8 mA	Negative Edge	45 MHz	16-SO 16-SOIC	Set(Preset) and Reset	5.25 V	4.75 V	JK Type	20 ns	15 pF	5.3 mm	0.209 in	Surface Mount	70 °C	6 mA	2
Texas Instruments SN74LS112AN	Complementary	1 bits	400 µA	8 mA	Negative Edge	45 MHz	16-DIP 16-PDIP	Set(Preset) and Reset	5.25 V	4.75 V	JK Type	20 ns	15 pF	7.62 mm	0.3 in	Through Hole	70 °C	6 mA	2
Texas Instruments SN74LS112AD	Complementary	1 bits	400 µA	8 mA	Negative Edge	45 MHz	16-SOIC	Set(Preset) and Reset	5.25 V	4.75 V	JK Type	20 ns	15 pF	3.9 mm	0.154 in	Surface Mount	70 °C	6 mA	2