CDCDB400 Series
4-output clock buffer for PCIe® Gen 1 to Gen 6
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
4-output clock buffer for PCIe® Gen 1 to Gen 6
| Part | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Mounting Type | Operating Temperature [Max] | Operating Temperature [Min] | Supplier Device Package | Input | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Package / Case | Frequency - Max [Max] | Type | Number of Circuits | Output |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCDB400RHBR | 3.6 V | 3 V | Surface Mount | 105 °C | -40 °C | 32-VQFN (5x5) | HCSL | 4 | 1 | 32-VFQFN Exposed Pad | 250 MHz | Clock Buffer | 1 | Clock, HCSL | ||
Texas Instruments CDCDB400RHBT | 3.6 V | 3 V | Surface Mount | 105 °C | -40 °C | 32-VQFN (5x5) | HCSL | 4 | 1 | 32-VFQFN Exposed Pad | 250 MHz | Clock Buffer | 1 | Clock, HCSL |
Key Features
• 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations4 hardware output enable (OE#) controlsAdditive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)Supports Common Clock (CC) and Individual Reference (IR) architecturesSpread spectrum-compatibleOutput-to-output skew: < 50 psInput-to-output delay: < 3 nsFail-safe inputProgrammable output slew rate control3 selectable SMBus addresses3.3-V core and IO supply voltagesHardware-controlled low power mode (PD#)Current consumption: 46 mA maximum5-mm × 5-mm, 32-pin VQFN package4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations4 hardware output enable (OE#) controlsAdditive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)Supports Common Clock (CC) and Individual Reference (IR) architecturesSpread spectrum-compatibleOutput-to-output skew: < 50 psInput-to-output delay: < 3 nsFail-safe inputProgrammable output slew rate control3 selectable SMBus addresses3.3-V core and IO supply voltagesHardware-controlled low power mode (PD#)Current consumption: 46 mA maximum5-mm × 5-mm, 32-pin VQFN package
Description
AI
The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.
The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.