74LVC841 Series

10-Bit Bus-Interface D-Type Latch With 3-State Outputs

Catalog(4 parts)

Part	Independent Circuits▲▼	Output Type	Voltage - Supply▲▼	Voltage - Supply▲▼	Package / Case▲▼	Package / Case▲▼	Package / Case	Supplier Device Package	Circuit	Mounting Type	Delay Time - Propagation▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Logic Type	Package / Case▲▼	Package / Case▲▼	Package / Case▲▼	Package / Case▲▼
Texas Instruments SN74LVC841APWT D-Type Transparent Latch 1 Channel 10:10 IC Tri-State 24-TSSOP	1 ul	Tri-State	3.5999999046325684 V	1.649999976158142 V	0.004399999976158142 m	0.004394200164824724 m	24-TSSOP	24-TSSOP	10:10	Surface Mount	2.7000000013543964e-9 s	-40 °C	85 °C	0.024000000208616257 A	0.024000000208616257 A	D-Type Transparent Latch
Texas Instruments SN74LVC841ADGVR D-Type Transparent Latch 1 Channel 10:10 IC Tri-State 24-TVSOP	1 ul	Tri-State	3.5999999046325684 V	1.649999976158142 V			24-TFSOP (0.173", 4.40mm Width)	24-TVSOP	10:10	Surface Mount	2.7000000013543964e-9 s	-40 °C	85 °C	0.024000000208616257 A	0.024000000208616257 A	D-Type Transparent Latch	0.004394200164824724 m	0.004399999976158142 m
Texas Instruments SN74LVC841ADWR D-Type Transparent Latch 1 Channel 10:10 IC Tri-State 24-SOIC	1 ul	Tri-State	3.5999999046325684 V	1.649999976158142 V			24-SOIC	24-SOIC	10:10	Surface Mount	2.7000000013543964e-9 s	-40 °C	85 °C	0.024000000208616257 A	0.024000000208616257 A	D-Type Transparent Latch			0.007499999832361937 m	0.007493000011891127 m
Texas Instruments SN74LVC841APWR D-Type Transparent Latch 1 Channel 10:10 IC Tri-State 24-TSSOP	1 ul	Tri-State	3.5999999046325684 V	1.649999976158142 V	0.004399999976158142 m	0.004394200164824724 m	24-TSSOP	24-TSSOP	10:10	Surface Mount	2.7000000013543964e-9 s	-40 °C	85 °C	0.024000000208616257 A	0.024000000208616257 A	D-Type Transparent Latch

Key Features

• Operates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)Latch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Operates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)Latch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCCoperation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCCoperation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.