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LMK04828-EP Series

Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c

PartPackage / CaseMounting TypeSupplier Device Package
Texas Instruments
LMK04828SNKDREP
Texas Instruments
LMK04828SNKDTEP
64-WFQFN Exposed Pad
Surface Mount
64-WQFN (9x9)

Key Features

EP FeaturesGold BondwiresTemperature Range: –55 to +105 °CLead Finish SnPbMaximum Distribution Frequency: 3.2 GHzJESD204B SupportUltra-Low RMS Jitter88-fs RMS Jitter (12 kHz to 20 MHz)91-fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks From PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.2 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2Up to 1 Buffered VCXO/Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableMulti-Mode: Dual PLL, Single PLL, and Clock DistributionDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switchover ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(Even and Odd)Precision Digital Delay, Dynamically Adjustable25-ps Step Analog Delay3.15-V to 3.45-V OperationPackage: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)EP FeaturesGold BondwiresTemperature Range: –55 to +105 °CLead Finish SnPbMaximum Distribution Frequency: 3.2 GHzJESD204B SupportUltra-Low RMS Jitter88-fs RMS Jitter (12 kHz to 20 MHz)91-fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks From PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.2 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2Up to 1 Buffered VCXO/Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableMulti-Mode: Dual PLL, Single PLL, and Clock DistributionDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switchover ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(Even and Odd)Precision Digital Delay, Dynamically Adjustable25-ps Step Analog Delay3.15-V to 3.45-V OperationPackage: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

Description

AI
The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees. The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.