CLVC2G125 Series
Automotive 2-ch, 1.65-V to 5.5-V buffers with 3-state outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Automotive 2-ch, 1.65-V to 5.5-V buffers with 3-state outputs
| Part | Number of Bits per Element | Grade | Number of Elements [custom] | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Qualification | Mounting Type | Output Type | Operating Temperature [Max] | Operating Temperature [Min] | Logic Type | Package / Case | Package / Case | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CLVC2G125IDCURQ1 | 1 | Automotive | 2 | 32 mA | 32 mA | AEC-Q100 | Surface Mount | 3-State | 85 °C | -40 °C | Buffer, Non-Inverting | 0.091 in | 8-VFSOP | 2.3 mm | 5.5 V | 1.65 V |
Key Features
• Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.3 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIQualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.3 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class II
Description
AI
The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.