74ALVCH374 Series
Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(4 parts)
| Part | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Clock Frequency▲▼ | Number of Bits per Element▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Input Capacitance▲▼ | Supplier Device Package | Package / Case▲▼ | Package / Case | Current - Quiescent (Iq)▲▼ | Function | Operating Temperature▲▼ | Operating Temperature▲▼ | Mounting Type | Number of Elements▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Type | Trigger Type | Output Type | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74ALVCH374DWFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) | 0.024000000208616257 A | 0.024000000208616257 A | 150000000 Hz | 8 ul | 3.6000000758207307e-9 s | 4.999999980020986e-12 F | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 0.000009999999747378752 A | Standard | 85 °C | -40 °C | Surface Mount | 1 ul | 3.5999999046325684 V | 1.649999976158142 V | D-Type | Positive Edge | Tri-State, Non-Inverted | |
Texas Instruments SN74ALVCH374DBRFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-SSOP (0.209", 5.30mm Width) | 0.024000000208616257 A | 0.024000000208616257 A | 150000000 Hz | 8 ul | 3.6000000758207307e-9 s | 4.999999980020986e-12 F | 20-SSOP | 0.0052999998442828655 m, 0.005308600142598152 m | 20-SSOP | 0.000009999999747378752 A | Standard | 85 °C | -40 °C | Surface Mount | 1 ul | 3.5999999046325684 V | 1.649999976158142 V | D-Type | Positive Edge | Tri-State, Non-Inverted | |
Texas Instruments SN74ALVCH374PWRFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width) | 0.024000000208616257 A | 0.024000000208616257 A | 150000000 Hz | 8 ul | 3.6000000758207307e-9 s | 4.999999980020986e-12 F | 20-TSSOP | 0.004394200164824724 m | 20-TSSOP | 0.000009999999747378752 A | Standard | 85 °C | -40 °C | Surface Mount | 1 ul | 3.5999999046325684 V | 1.649999976158142 V | D-Type | Positive Edge | Tri-State, Non-Inverted | 0.004399999976158142 m |
Texas Instruments SN74ALVCH374DWRFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) | 0.024000000208616257 A | 0.024000000208616257 A | 150000000 Hz | 8 ul | 3.6000000758207307e-9 s | 4.999999980020986e-12 F | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 0.000009999999747378752 A | Standard | 85 °C | -40 °C | Surface Mount | 1 ul | 3.5999999046325684 V | 1.649999976158142 V | D-Type | Positive Edge | Tri-State, Non-Inverted |
Key Features
• Operates From 1.65 V to 3.6 VMax tpdof 3.6 ns at 3.3 V±24-mA Output Drive at 3.3 VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Operates From 1.65 V to 3.6 VMax tpdof 3.6 ns at 3.3 V±24-mA Output Drive at 3.3 VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
Description
AI
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.