Catalog(13 parts)
Part | Mounting Type | Output Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Delay Time - Propagation▲▼ | Circuit | Current - Output High, Low▲▼ | Package / Case▲▼ | Package / Case | Independent Circuits▲▼ | Logic Type | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case▲▼ |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C | ||
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.003911599982529879 m | 20-SSOP | 1 ul | D-Type Transparent Latch | 20-SSOP | -40 °C | 85 °C | 0.003899999894201755 m | |
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C | ||
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.003911599982529879 m | 20-SSOP | 1 ul | D-Type Transparent Latch | 20-SSOP/QSOP | -40 °C | 85 °C | 0.003899999894201755 m | |
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C | ||
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C | ||
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C | ||
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C | ||
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.003911599982529879 m | 20-SSOP | 1 ul | D-Type Transparent Latch | 20-SSOP | -40 °C | 85 °C | 0.003899999894201755 m | |
Surface Mount | Tri-State | 4.75 V | 5.25 V | 1.999999943436137e-9 s | 8:8 | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | 1 ul | D-Type Transparent Latch | 20-SOIC | -40 °C | 85 °C |
Key Features
• Function and Pinout Compatible With FCT and F LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Matched Rise and Fall TimesFully Compatible With TTL Input and Output Logic Levels3-State OutputsCY54FCT573T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT573T64-mA Output Sink Current32-mA Output Source CurrentFunction and Pinout Compatible With FCT and F LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Matched Rise and Fall TimesFully Compatible With TTL Input and Output Logic Levels3-State OutputsCY54FCT573T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT573T64-mA Output Sink Current32-mA Output Source Current
Description
AI
The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.