74FCT573 Series

Octal Transparent D-Type Latches with 3-State Outputs

Catalog

Octal Transparent D-Type Latches with 3-State Outputs

Part	Package Name	Current - Output High	Current - Output Low	Independent Circuits	Mounting Type	Delay Time - Propagation	Operating Temperature (Min)	Operating Temperature (Max)	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Logic Type	Output Type	Circuit	Package Length	Package Width
Texas Instruments CY74FCT573CTSOCG4	20-SOIC	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.295 in	7.5 mm
Texas Instruments CD74FCT573M
Texas Instruments CY74FCT573CTQCT	20-SSOP	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.154 in	3.9 mm
Texas Instruments CD74FCT573E
Texas Instruments CY74FCT573ATQC
Texas Instruments CY74FCT573CTSOCT	20-SOIC	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.295 in	7.5 mm
Texas Instruments CY74FCT573ATQCTE4	20-SSOP 20-SSOP/QSOP	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.154 in	3.9 mm
Texas Instruments CY74FCT573TSOC	20-SOIC	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.295 in	7.5 mm
Texas Instruments CY74FCT573CTSOC	20-SOIC	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.295 in	7.5 mm
Texas Instruments CY74FCT573TSOCT	20-SOIC	32 mA	64 mA	1	Surface Mount	2 ns	-40 °C	85 °C	5.25 V	4.75 V	D-Type Transparent Latch	Tri-State	8:8	0.295 in	7.5 mm

Catalog

Octal Transparent D-Type Latches with 3-State Outputs

Description

The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.