74AUCH16374 Series
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Clock Frequency▲▼ | Number of Elements▲▼ | Trigger Type | Mounting Type | Number of Bits per Element▲▼ | Type | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Current - Quiescent (Iq)▲▼ | Input Capacitance▲▼ | Function | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Supplier Device Package | Max Propagation Delay @ V, Max CL▲▼ | Output Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74AUCH16374DGGRFlip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width) | 250000000 Hz | 2 ul | Positive Edge | Surface Mount | 8 ul | D-Type | 0.006099999882280827 m | 48-TFSOP | 0.006095999851822853 m | 0.800000011920929 V | 2.700000047683716 V | 85 °C | -40 °C | 0.000019999999494757503 A | 2.9999999880125916e-12 F | Standard | 0.008999999612569809 A | 0.008999999612569809 A | 48-TSSOP | 2.199999959984211e-9 s | Tri-State, Non-Inverted |
250000000 Hz | 2 ul | Positive Edge | Surface Mount | 8 ul | D-Type | 56-VFBGA | 0.800000011920929 V | 2.700000047683716 V | 85 °C | -40 °C | 0.000019999999494757503 A | 2.9999999880125916e-12 F | Standard | 0.008999999612569809 A | 0.008999999612569809 A | 56-BGA Microstar Junior (7x4.5) | 2.199999959984211e-9 s | Tri-State, Non-Inverted |
Key Features
• Member of the Texas Instruments Widebus FamilyOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerantto Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 2.8 ns at 1.8 VLow Power Consumption, 20 µA Max ICC±8-mA Output Drive at 1.8 VBus Hold on Data Inputs Eliminates the Need for ExternalPullup/Pulldown ResistorsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus FamilyOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerantto Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 2.8 ns at 1.8 VLow Power Consumption, 20 µA Max ICC±8-mA Output Drive at 1.8 VBus Hold on Data Inputs Eliminates the Need for ExternalPullup/Pulldown ResistorsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.
Description
AI
This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.