CDCE949-Q1 Series

AEC-Q100 programmable 4-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs

Link to Manufacturer Page: https://www.ti.com/

Catalog

AEC-Q100 programmable 4-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs

Part	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Mounting Type	Divider/Multiplier	Operating Temperature [Max]	Operating Temperature [Min]	Number of Circuits	Qualification	Type	Output	Input	Package / Case [y]	Package / Case [y]	Package / Case	PLL	Supplier Device Package	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Frequency - Max [Max]	Grade
Texas Instruments CDCE949QPWRQ1	1	9	Surface Mount	Yes/No	125 °C	-40 °C	1	AEC-Q100	Spread Spectrum Clock Driver	LVCMOS	Crystal, LVCMOS	4.4 mm	0.173 "	24-TSSOP	Yes with Bypass	24-TSSOP			1.7 V	1.9 V	230 MHz	Automotive

Key Features

• Qualified for Automotive ApplicationsMember of Programmable Clock Generator FamilyCDCE913/CDCEL913: 1 PLLs, 3 OutputsCDCE925/CDCEL925: 2 PLLs, 5 OutputsCDCE937/CDCEL937: 3 PLLs, 7 OutputsCDCE949: 4 PLLs, 9 OutputsIn-System Programmability and EEPROMSerial Programmable Volatile RegisterNon-Volatile EEPROM to Store Customer SettingsHighly Flexible Clock DriverThree User-Definable Control Inputs [S0/S1/S2]; e.g,. SSC-Selection, Frequency Switching, Output Enable or Power DownGenerates Highly-Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Generates Common Clock Frequencies Used with TI DaVinci™, OMAP™, DSPsBlueTooth™, WLAN, Ethernet and GPSProgrammable SSC ModulationEnables 0-PPM Clock GenerationSelectable Output Frequency up to 230 MHzFlexible Input Clocking ConceptExternal Crystal: 8 to 32 MHzOn-Chip VCXO: Pull-Range ±150 ppmSingle-Ended LVCMOS up to 160 MHzLow-Noise PLL CoreIntegrated PLL Loop Filter ComponentsVery Low Period Jitter (typ 60 ps)Separate Output Supply Pins3.3 V and 2.5 V1.8 V Device Power SupplyLatch-Up Performace Meets 100 mAPer JESD 78, Class IWide Temperature Range –40°C to 125°CPackaged in TSSOPDevelopment and Programming Kit for Ease PLL Design and Programming(TI-Pro Clock)APPLICATIONSD-TV, HD-TV, STB, IP-STB, DVD-Player, DVD-Recorder, PrinterGeneral Purpose Frequency SynthesizingQualified for Automotive ApplicationsMember of Programmable Clock Generator FamilyCDCE913/CDCEL913: 1 PLLs, 3 OutputsCDCE925/CDCEL925: 2 PLLs, 5 OutputsCDCE937/CDCEL937: 3 PLLs, 7 OutputsCDCE949: 4 PLLs, 9 OutputsIn-System Programmability and EEPROMSerial Programmable Volatile RegisterNon-Volatile EEPROM to Store Customer SettingsHighly Flexible Clock DriverThree User-Definable Control Inputs [S0/S1/S2]; e.g,. SSC-Selection, Frequency Switching, Output Enable or Power DownGenerates Highly-Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Generates Common Clock Frequencies Used with TI DaVinci™, OMAP™, DSPsBlueTooth™, WLAN, Ethernet and GPSProgrammable SSC ModulationEnables 0-PPM Clock GenerationSelectable Output Frequency up to 230 MHzFlexible Input Clocking ConceptExternal Crystal: 8 to 32 MHzOn-Chip VCXO: Pull-Range ±150 ppmSingle-Ended LVCMOS up to 160 MHzLow-Noise PLL CoreIntegrated PLL Loop Filter ComponentsVery Low Period Jitter (typ 60 ps)Separate Output Supply Pins3.3 V and 2.5 V1.8 V Device Power SupplyLatch-Up Performace Meets 100 mAPer JESD 78, Class IWide Temperature Range –40°C to 125°CPackaged in TSSOPDevelopment and Programming Kit for Ease PLL Design and Programming(TI-Pro Clock)APPLICATIONSD-TV, HD-TV, STB, IP-STB, DVD-Player, DVD-Recorder, PrinterGeneral Purpose Frequency Synthesizing

Description

The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs. The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal. The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz. All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL. The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration (see theDefault device Configurationsection). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface. Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function. The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C. The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs. The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal. The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz. All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL. The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration (see theDefault device Configurationsection). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface. Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function. The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C.