SN74HC373A Series

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

Catalog

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Operating Temperature [Min]	Operating Temperature [Max]	Independent Circuits	Output Type	Delay Time - Propagation	Voltage - Supply [Min]	Voltage - Supply [Max]	Logic Type	Package / Case	Package / Case [y]	Package / Case [y]	Mounting Type	Circuit [custom]	Circuit [custom]	Package / Case	Package / Case	Package / Case [x]
Texas Instruments CD74HC373M96	7.8 mA	7.8 mA	20-SOIC	-55 °C	125 °C	1	Tri-State	30 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	Surface Mount	8	8
Texas Instruments SN74HC373NS	7.8 mA	7.8 mA	20-SO	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC			Surface Mount	8	8	0.209 "	5.3 mm
Texas Instruments SN74HC373N	7.8 mA	7.8 mA	20-PDIP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-DIP			Through Hole	8	8	0.3 in	7.62 mm
Texas Instruments SN74HC373DBR	7.8 mA	7.8 mA	20-SSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-SSOP			Surface Mount	8	8
Texas Instruments SN74HC373PW	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in
Texas Instruments SN74HC373PWRG4	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in
Texas Instruments CD74HC373M	7.8 mA	7.8 mA	20-SOIC	-55 °C	125 °C	1	Tri-State	30 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	Surface Mount	8	8
Texas Instruments SN74HC373DW	7.8 mA	7.8 mA	20-SOIC	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	Surface Mount	8	8
Texas Instruments SN74HC373PWT	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in
Texas Instruments SN74HC373PWRE4	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in

Catalog

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

Key Features

• Wide operating voltage range of 2V to 6VHigh-current 3-state true outputs can drive up to 15 LSTTL loadsLow power consumption, 80µA max ICCTypical tpd = 13ns±6mA output drive at 5VLow input current of 1µA maxEight high-current latches in a single packageFull parallel access for loadingWide operating voltage range of 2V to 6VHigh-current 3-state true outputs can drive up to 15 LSTTL loadsLow power consumption, 80µA max ICCTypical tpd = 13ns±6mA output drive at 5VLow input current of 1µA maxEight high-current latches in a single packageFull parallel access for loading

Description

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the SN74HC373A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the SN74HC373A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.