74HC670 Series

High Speed CMOS Logic 4-by-4 Register File

Catalog(4 parts)

Part	Voltage Supply Source	Mounting Type	Independent Circuits▲▼	Type	Package / Case	Package / Case▲▼	Supplier Device Package	Voltage - Supply▲▼	Voltage - Supply▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Circuit
Texas Instruments CD74HC670MT Register File 1 x 1:1 16-SOIC	Single Supply	Surface Mount	4 ul	Register File	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	16-SOIC	2 V	6 V	-55 °C	125 °C	1 x 1:1
Texas Instruments CD74HC670M Register File 1 x 1:1 16-SOIC	Single Supply	Surface Mount	4 ul	Register File	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	16-SOIC	2 V	6 V	-55 °C	125 °C	1 x 1:1
Texas Instruments CD74HC670E Register File 1 x 1:1 16-PDIP	Single Supply	Through Hole	4 ul	Register File	16-DIP	0.007619999814778566 m, 0.007619999814778566 m	16-PDIP	2 V	6 V	-55 °C	125 °C	1 x 1:1
Texas Instruments CD74HC670M96 Register File 1 x 1:1 16-SOIC	Single Supply	Surface Mount	4 ul	Register File	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	16-SOIC	2 V	6 V	-55 °C	125 °C	1 x 1:1

Key Features

• Simultaneous and Independent Read and Write OperationsExpandable to 512 Words of n-BitsThree-State OutputsOrganized as 4 Words x 4 Bits WideBuffered InputsTypical Read Time = 16ns for ’HC670 VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range... –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHSimultaneous and Independent Read and Write OperationsExpandable to 512 Words of n-BitsThree-State OutputsOrganized as 4 Words x 4 Bits WideBuffered InputsTypical Read Time = 16ns for ’HC670 VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range... –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOH

Description

The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE\) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE\) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE\) is low. The output is in the high impedance state when the (RE\) is high. Outputs can be tied together to increase the word capacity to 512 x 4 bits. The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE\) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE\) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE\) is low. The output is in the high impedance state when the (RE\) is high. Outputs can be tied together to increase the word capacity to 512 x 4 bits.