TPS70848 Series

The TPS708xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 250 mA and 125 mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal toEN1orEN2(enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to bothEN1andEN2, both regulators enter sleep mode, thereby reducing the input current to 2 µA at TJ= +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS708xx features aRESET(SVS, POR, or power on reset).RESEToutput initiates a reset in the event of an undervoltage condition.RESETalso indicates the status of the manual reset pin (MR). WhenMRis in the logic high state,RESETgoes to a high impedance state after a 120-ms delay. To monitor VOUT1, the PG1 output pin can be connected toMR. To monitor VOUT2, the PG2 output pin can be connected toMR. The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1reaches 2.5V. The TPS708xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 250 mA and 125 mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal toEN1orEN2(enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to bothEN1andEN2, both regulators enter sleep mode, thereby reducing the input current to 2 µA at TJ= +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS708xx features aRESET(SVS, POR, or power on reset).RESEToutput initiates a reset in the event of an undervoltage condition.RESETalso indicates the status of the manual reset pin (MR). WhenMRis in the logic high state,RESETgoes to a high impedance state after a 120-ms delay. To monitor VOUT1, the PG1 output pin can be connected toMR. To monitor VOUT2, the PG2 output pin can be connected toMR. The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1reaches 2.5V.