Catalog(4 parts)
| Part | Number of Elements▲▼ | Function | Trigger Type | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Clock Frequency▲▼ | Number of Bits per Element▲▼ | Type | Current - Quiescent (Iq)▲▼ | Mounting Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Output Type▲▼ | Input Capacitance▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74LVC2G80DCURFlip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width) | 2 ul | Standard | Positive Edge | 0.002311399905011058 m | 8-VFSOP | 0.002300000051036477 m | 160000000 Hz | 1 ul | D-Type | 0.000004999999873689376 A | Surface Mount | -40 °C | 125 °C | 5.5 V | 1.649999976158142 V | 27.030000686645508 °C/W | 3.4999999860146898e-12 F | 4.4999999282424605e-9 s | 0.03200000151991844 A | 0.03200000151991844 A | |
Texas Instruments SN74LVC2G80DCTRFlip Flop 2 Element D-Type 1 Bit Positive Edge 8-LSSOP, 8-MSOP (0.110", 2.80mm Width) | 2 ul | Standard | Positive Edge | 160000000 Hz | 1 ul | D-Type | 0.000004999999873689376 A | Surface Mount | -40 °C | 125 °C | 5.5 V | 1.649999976158142 V | 27.030000686645508 °C/W | 3.4999999860146898e-12 F | 4.4999999282424605e-9 s | 0.03200000151991844 A | 0.03200000151991844 A | SM8 | |||
Texas Instruments SN74LVC2G80DCURG4Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width) | 2 ul | Standard | Positive Edge | 0.002311399905011058 m | 8-VFSOP | 0.002300000051036477 m | 160000000 Hz | 1 ul | D-Type | 0.000004999999873689376 A | Surface Mount | -40 °C | 125 °C | 5.5 V | 1.649999976158142 V | 27.030000686645508 °C/W | 3.4999999860146898e-12 F | 4.4999999282424605e-9 s | 0.03200000151991844 A | 0.03200000151991844 A | |
Texas Instruments SN74LVC2G80DCTRG4Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-LSSOP, 8-MSOP (0.110", 2.80mm Width) | 2 ul | Standard | Positive Edge | 160000000 Hz | 1 ul | D-Type | 0.000004999999873689376 A | Surface Mount | -40 °C | 125 °C | 5.5 V | 1.649999976158142 V | 27.030000686645508 °C/W | 3.4999999860146898e-12 F | 4.4999999282424605e-9 s | 0.03200000151991844 A | 0.03200000151991844 A | SM8 |
Key Features
• Available in the Texas InstrumentsNanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.2 ns at 3.3 VLow Power Consumption, 10-μA Max ICCTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffFeature Supports Live Insertion, Partial-Power-Down and Back Drive ProtectionMode OperationLatch-Up Performance Exceeds 100 mAPer JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in the Texas InstrumentsNanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.2 ns at 3.3 VLow Power Consumption, 10-μA Max ICCTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffFeature Supports Live Insertion, Partial-Power-Down and Back Drive ProtectionMode OperationLatch-Up Performance Exceeds 100 mAPer JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
Description
AI
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.