CDCLVP111-EP Series
HiRel, 1:10 LVPECL buffer with selectable input
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
HiRel, 1:10 LVPECL buffer with selectable input
| Part | Frequency - Max [Max] | Mounting Type | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Supplier Device Package | Output | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] | Type | Operating Temperature [Min] | Operating Temperature [Max] | Number of Circuits | Input | Differential - Input:Output [custom] | Differential - Input:Output [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP111MVFREP | 3.5 GHz | Surface Mount | 2 | 10 | 32-LQFP (7x7) | LVPECL | 32-LQFP | 3.8 V | 2.375 V | Fanout Buffer (Distribution), Multiplexer | -55 °C | 125 °C | 1 | CML, LVDS, LVPECL, SSTL |
Key Features
• Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECLFully Compatible With LVECL and LVPECLSupports a Wide Supply Voltage Range From 2.375 V to 3.8 VSelectable Clock Input Through CLK_SELLow-Output Skew (Typ 15 ps) for Clock-Distribution ApplicationsAdditive Jitter Less Than 1 psPropagation Delay Less Than 355 psOpen Input Default StateLVDS, CML, SSTL input compatibleVBBReference Voltage Output for Single-Ended ClockingAvailable in a 32-Pin LQFP PackageFrequency Range From DC to 3.5 GHzPin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECLFully Compatible With LVECL and LVPECLSupports a Wide Supply Voltage Range From 2.375 V to 3.8 VSelectable Clock Input Through CLK_SELLow-Output Skew (Typ 15 ps) for Clock-Distribution ApplicationsAdditive Jitter Less Than 1 psPropagation Delay Less Than 355 psOpen Input Default StateLVDS, CML, SSTL input compatibleVBBReference Voltage Output for Single-Ended ClockingAvailable in a 32-Pin LQFP PackageFrequency Range From DC to 3.5 GHzPin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111
Description
AI
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.
The VBBreference voltage output is used if single-ended input operation is required. In this case, the VBBpin should be connected toCLK0and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP111 is characterized for operation from –55°C to 125°C.
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.
The VBBreference voltage output is used if single-ended input operation is required. In this case, the VBBpin should be connected toCLK0and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP111 is characterized for operation from –55°C to 125°C.