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74LVC2G132 Series

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Manufacturer: Texas Instruments

Catalog(5 parts)

PartNumber of Circuits▲▼Operating Temperature▲▼Operating Temperature▲▼Input Logic Level - High▲▼Input Logic Level - High▲▼Package / Case▲▼Package / CasePackage / Case▲▼Input Logic Level - Low▲▼Input Logic Level - Low▲▼Voltage - Supply▲▼Voltage - Supply▲▼Mounting TypeLogic TypeFeaturesNumber of Inputs▲▼Current - Quiescent (Max)▲▼Current - Output High, Low▲▼Current - Output High, Low▲▼Max Propagation Delay @ V, Max CL▲▼Supplier Device Package
Texas Instruments
74LVC2G132DCURE4
NAND Gate IC 2 Channel Schmitt Trigger 8-VSSOP
2 ul
125 °C
-40 °C
1.159999966621399 V
3.3299999237060547 V
0.002311399905011058 m
8-VFSOP
0.002300000051036477 m
1.8700000047683716 V
0.38999998569488525 V
5.5 V
1.649999976158142 V
Surface Mount
NAND Gate
Schmitt Trigger
2 ul
0.000009999999747378752 A
0.03200000151991844 A
0.03200000151991844 A
6.000000052353016e-9 s
Texas Instruments
SN74LVC2G132DCUT
NAND Gate IC 2 Channel Schmitt Trigger 8-VSSOP
2 ul
125 °C
-40 °C
1.159999966621399 V
3.3299999237060547 V
0.002311399905011058 m
8-VFSOP
0.002300000051036477 m
1.8700000047683716 V
0.38999998569488525 V
5.5 V
1.649999976158142 V
Surface Mount
NAND Gate
Schmitt Trigger
2 ul
0.000009999999747378752 A
0.03200000151991844 A
0.03200000151991844 A
4.999999969612645e-9 s
Texas Instruments
SN74LVC2G132DCTR
NAND Gate IC 2 Channel Schmitt Trigger SM8
2 ul
125 °C
-40 °C
1.159999966621399 V
3.3299999237060547 V
1.8700000047683716 V
0.38999998569488525 V
5.5 V
1.649999976158142 V
Surface Mount
NAND Gate
Schmitt Trigger
2 ul
0.000009999999747378752 A
0.03200000151991844 A
0.03200000151991844 A
4.999999969612645e-9 s
SM8
Texas Instruments
SN74LVC2G132DCUR
NAND Gate IC 2 Channel Schmitt Trigger 8-VSSOP
2 ul
125 °C
-40 °C
1.159999966621399 V
3.3299999237060547 V
0.002311399905011058 m
8-VFSOP
0.002300000051036477 m
1.8700000047683716 V
0.38999998569488525 V
5.5 V
1.649999976158142 V
Surface Mount
NAND Gate
Schmitt Trigger
2 ul
0.000009999999747378752 A
0.03200000151991844 A
0.03200000151991844 A
4.999999969612645e-9 s
Texas Instruments
SN74LVC2G132YEPR
NAND Gate IC 2 Channel Schmitt Trigger 8-DSBGA (1.9x0.9)
2 ul
85 °C
-40 °C
1.159999966621399 V
3.3299999237060547 V
8-XFBGA, DSBGA
1.8700000047683716 V
0.38999998569488525 V
5.5 V
1.649999976158142 V
Surface Mount
NAND Gate
Schmitt Trigger
2 ul
0.000009999999747378752 A
0.03200000151991844 A
0.03200000151991844 A
4.999999969612645e-9 s
8-DSBGA (1.9x0.9)

Key Features

• Available in Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 5.3 ns at 3.3 VLow Power Consumption, 10-μA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial Power Down Mode, and Back Drive ProtectionSupport Translation Down (5V to 3.3V and 3.3V to 1.8V)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 5.3 ns at 3.3 VLow Power Consumption, 10-μA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial Power Down Mode, and Back Drive ProtectionSupport Translation Down (5V to 3.3V and 3.3V to 1.8V)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

AI
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.