CD74HCT03 Series
4-ch, 2-input, 4.5-V to 5.5-V NAND gates with TTL-compatible CMOS inputs and open-drain outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
4-ch, 2-input, 4.5-V to 5.5-V NAND gates with TTL-compatible CMOS inputs and open-drain outputs
Part | Mounting Type | Operating Temperature [Min] | Operating Temperature [Max] | Package / Case | Package / Case | Package / Case | Features | Max Propagation Delay @ V, Max CL | Input Logic Level - Low | Number of Circuits | Current - Output High, Low | Current - Output High, Low | Number of Inputs | Voltage - Supply [Max] | Voltage - Supply [Min] | Logic Type |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HCT03E | Through Hole | -55 °C | 125 °C | 14-DIP | 7.62 mm | 0.3 in | Open Drain | 24 ns | 0.8 V | 4 | - | 4 mA | 2 | 5.5 V | 4.5 V | NAND Gate |
Texas Instruments CD74HCT03M | Surface Mount | -55 °C | 125 °C | 14-SOIC | 3.9 mm | 0.154 in | Open Drain | 24 ns | 0.8 V | 4 | - | 4 mA | 2 | 5.5 V | 4.5 V | NAND Gate |
Texas Instruments CD74HCT03M96 | Surface Mount | -55 °C | 125 °C | 14-SOIC | 3.9 mm | 0.154 in | Open Drain | 24 ns | 0.8 V | 4 | - | 4 mA | 2 | 5.5 V | 4.5 V | NAND Gate |
Key Features
• LSTTL input logic compatibleVIL(max)= 0.8 V, VIH(min)= 2 VCMOS input logic compatibleII≤ 1 µA at VOL, VOHBuffered inputs4.5 V to 5.5 V operationWide operating temperature range: -55°C to +125°CSupports fanout up to 10 LSTTL loadsSignificant power reduction compared to LSTTL logic ICsLSTTL input logic compatibleVIL(max)= 0.8 V, VIH(min)= 2 VCMOS input logic compatibleII≤ 1 µA at VOL, VOHBuffered inputs4.5 V to 5.5 V operationWide operating temperature range: -55°C to +125°CSupports fanout up to 10 LSTTL loadsSignificant power reduction compared to LSTTL logic ICs
Description
AI
This device contains four independent 2-input NAND gates with open-drain outputs. Each gate performs the Boolean function Y =A ● Bin positive logic.
This device contains four independent 2-input NAND gates with open-drain outputs. Each gate performs the Boolean function Y =A ● Bin positive logic.