UCD7232 Series

The UCD7232 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMONpin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 207°. The UCD7232 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMONpin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 207°.