74AC112 Series
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
Manufacturer: Texas Instruments
Catalog(3 parts)
| Part | Mounting Type | Clock Frequency▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Current - Quiescent (Iq)▲▼ | Trigger Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Type | Function | Output Type | Supplier Device Package | Package / Case | Package / Case▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Input Capacitance▲▼ | Number of Elements▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Number of Bits per Element▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74AC112MFlip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width) | Surface Mount | 100000000 Hz | 0.024000000208616257 A | 0.024000000208616257 A | 0.000003999999989900971 A | Negative Edge | 1.5 V | 5.5 V | JK Type | Reset, Set(Preset) | Complementary | 16-SOIC | 16-SOIC | 0.003911599982529879 m, 3.900000095367432 ul | -55 °C | 125 °C | 9.999999960041972e-12 F | 2 ul | 1.0299999964047402e-8 s | 1 ul |
Texas Instruments CD74AC112M96G4Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width) | Surface Mount | 100000000 Hz | 0.024000000208616257 A | 0.024000000208616257 A | 0.000003999999989900971 A | Negative Edge | 1.5 V | 5.5 V | JK Type | Reset, Set(Preset) | Complementary | 16-SOIC | 16-SOIC | 0.003911599982529879 m, 3.900000095367432 ul | -55 °C | 125 °C | 9.999999960041972e-12 F | 2 ul | 1.0299999964047402e-8 s | 1 ul |
Through Hole | 100000000 Hz | 0.024000000208616257 A | 0.024000000208616257 A | 0.000003999999989900971 A | Negative Edge | 1.5 V | 5.5 V | JK Type | Reset, Set(Preset) | Complementary | 16-PDIP | 16-DIP | 0.007619999814778566 m, 0.007619999814778566 m | -55 °C | 125 °C | 9.999999960041972e-12 F | 2 ul | 1.0299999964047402e-8 s | 1 ul |
Key Features
• AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply VoltageSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply VoltageSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
Description
AI
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.