Catalog(2 parts)
| Part | Mounting Type | Supplier Device Package | Package / Case▲▼ | Package / Case | Logic Type | Circuit | Output Type | Delay Time - Propagation▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Current - Output High, Low▲▼ | Independent Circuits▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Surface Mount | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | D-Type Transparent Latch | 8:8 | Tri-State | 8.599999823388771e-9 s | 5.5 V | 4.5 V | 70 °C | 0 °C | 0.003000000026077032 A, 0.024000000208616257 A | 1 ul | |||
Through Hole | 20-PDIP | 20-DIP | D-Type Transparent Latch | 8:8 | Tri-State | 8.599999823388771e-9 s | 5.5 V | 4.5 V | 70 °C | 0 °C | 0.003000000026077032 A, 0.024000000208616257 A | 1 ul | 0.007619999814778566 m | 0.007619999814778566 m |
Key Features
• Eight Latches in a Single Package3-State Bus-Driving True OutputsFull Parallel Access for LoadingBuffered Control InputsPackage Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPsEight Latches in a Single Package3-State Bus-Driving True OutputsFull Parallel Access for LoadingBuffered Control InputsPackage Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
Description
AI
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ´F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output enableinput does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54F573 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F573 is characterized for operation from 0°C to 70°C.
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ´F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output enableinput does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54F573 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F573 is characterized for operation from 0°C to 70°C.