CDCDB803 Series

8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses

Link to Manufacturer Page: https://www.ti.com/

Catalog

8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses

Part	Number of Circuits	Frequency - Max [Max]	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Output	Mounting Type	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Input	Type	Supplier Device Package
Texas Instruments CDCDB803RSLR	1	250 MHz	1	8	105 °C	-40 °C	Clock, HCSL	Surface Mount	48-VFQFN Exposed Pad	3.6 V	3 V	HCSL	Clock Buffer	48-VQFN (6x6)
Texas Instruments CDCDB803RSLT	1	250 MHz	1	8	105 °C	-40 °C	Clock, HCSL	Surface Mount	48-VFQFN Exposed Pad	3.6 V	3 V	HCSL	Clock Buffer	48-VQFN (6x6)
Texas Instruments CDCDB803ERSLR	1	250 MHz	1	8	105 °C	-40 °C	Clock, HCSL	Surface Mount	48-VFQFN Exposed Pad	3.6 V	3 V	HCSL	Clock Buffer	48-VQFN (6x6)
Texas Instruments CDCDB803ERSLT	1	250 MHz	1	8	105 °C	-40 °C	Clock, HCSL	Surface Mount	48-VFQFN Exposed Pad	3.6 V	3 V	HCSL	Clock Buffer	48-VQFN (6x6)

Key Features

• 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations8 hardware output enable (OE#) controlsAdditive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)Supports Common Clock (CC) and Individual Reference (IR) architecturesSpread spectrum-compatibleOutput-to-output skew: < 50 psInput-to-output delay: < 3 nsFail-safe inputProgrammable output slew rate control9 selectable SMBus addresses3.3-V core and IO supply voltagesHardware-controlled low power mode (PD#)Current consumption: 72 mA maximum6-mm × 6-mm, 48-pin VQFN package8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations8 hardware output enable (OE#) controlsAdditive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)Supports Common Clock (CC) and Individual Reference (IR) architecturesSpread spectrum-compatibleOutput-to-output skew: < 50 psInput-to-output delay: < 3 nsFail-safe inputProgrammable output slew rate control9 selectable SMBus addresses3.3-V core and IO supply voltagesHardware-controlled low power mode (PD#)Current consumption: 72 mA maximum6-mm × 6-mm, 48-pin VQFN package

Description

The CDCDB803 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package. The CDCDB803 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.