Catalog(2 parts)
| Part | Operating Temperature▲▼ | Operating Temperature▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Number of Bits per Element▲▼ | Output Type | Number of Elements▲▼ | Mounting Type | Supplier Device Package | Package / Case | Package / Case▲▼ | Package / Case▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74LVCH16952ADGGRTransceiver, Non-Inverting 2 Element 8 Bit per Element 3-State Output 56-TSSOP | 85 °C | -40 °C | 0.024000000208616257 A | 0.024000000208616257 A | 8 ul | 3-State | 2 ul | Surface Mount | 56-TSSOP | 56-TFSOP | 0.006099999882280827 m | 0.006095999851822853 m | 3.5999999046325684 V | 1.649999976158142 V | ||
Texas Instruments SN74LVCH16952ADLTransceiver, Non-Inverting 2 Element 8 Bit per Element 3-State Output 56-SSOP | 85 °C | -40 °C | 0.024000000208616257 A | 0.024000000208616257 A | 8 ul | 3-State | 2 ul | Surface Mount | 56-SSOP | 56-BSSOP | 3.5999999046325684 V | 1.649999976158142 V | 0.007493000011891127 m | 0.007499999832361937 m |
Key Features
• Member of the Texas Instruments Widebus™ FamilyOperates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.6 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyOperates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.6 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.
Description
AI
This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCH16952A contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CEAB\ or CEBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCH16952A contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CEAB\ or CEBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.