CD74FCT273 Series
BiCMOS FCT Interface Logic Octal D-Type Flip-Flops with Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
BiCMOS FCT Interface Logic Octal D-Type Flip-Flops with Reset
| Part | Max Propagation Delay @ V, Max CL | Clock Frequency | Number of Elements [custom] | Type | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type | Trigger Type | Voltage - Supply [Min] | Voltage - Supply [Max] | Output Type | Package / Case | Package / Case | Supplier Device Package | Input Capacitance | Current - Quiescent (Iq) | Number of Bits per Element | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74FCT273M | 7 ns | 70 MHz | 1 | D-Type | 15 mA | 48 mA | 70 °C | 0 °C | Surface Mount | Positive Edge | 4.75 V | 5.25 V | Non-Inverted | 0.295 in, 7.5 mm | 20-SOIC | 20-SOIC | 10 pF | 8 ÁA | 8 | ||
Texas Instruments CD74FCT273E | 7 ns | 70 MHz | 1 | D-Type | 15 mA | 48 mA | 70 °C | 0 °C | Through Hole | Positive Edge | 4.75 V | 5.25 V | Non-Inverted | 20-DIP | 20-PDIP | 8 ÁA | 8 | 0.3 in | 7.62 mm |
Key Features
• BiCMOS Technology With Low Quiescent PowerBuffered InputsDirect Clear Input48-mA Output Sink CurrentOutput Voltage Swing Limited to 3.7 VControlled Output Edge RatesInput/Output Isolation From VCCSCR Latch-Up-Resistant BiCMOS Process and Circuit DesignApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsPackage Options Include Plastic Small-Outline (M) Package and Standard Plastic (E) DIPBiCMOS Technology With Low Quiescent PowerBuffered InputsDirect Clear Input48-mA Output Sink CurrentOutput Voltage Swing Limited to 3.7 VControlled Output Edge RatesInput/Output Isolation From VCCSCR Latch-Up-Resistant BiCMOS Process and Circuit DesignApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsPackage Options Include Plastic Small-Outline (M) Package and Standard Plastic (E) DIP
Description
AI
The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR\) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCCbounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR\). The outputs are placed in a low state when CLR\ is taken low, independent of the CLK.
The CD74FCT273 is characterized for operation from 0°C to 70°C.
The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR\) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCCbounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR\). The outputs are placed in a low state when CLR\ is taken low, independent of the CLK.
The CD74FCT273 is characterized for operation from 0°C to 70°C.