ADC12J4000 Series
12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Number of Inputs▲▼ | Sampling Rate (Per Second)▲▼ | Data Interface | Input Type | Architecture | Package / Case | Mounting Type | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Configuration | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Reference Type | Number of Bits▲▼ | Number of A/D Converters▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Supplier Device Package | Ratio - S/H:ADC |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC12J4000NKER12 Bit Analog to Digital Converter 1 Input 1 Folding Interpolating 68-VQFN (10x10) | 1 ul | 4000000000 Ω | JESD204B | Differential | Folding Interpolating | 68-VFQFN Exposed Pad | Surface Mount | 1.2599999904632568 V | 1.1399999856948853 V | S/H-ADC | 1.1399999856948853 V, 1.7999999523162842 V | 1.2599999904632568 V, 2 V | Internal | 12 ul | 1 ul | -40 °C | 85 °C | 68-VQFN (10x10) | 1:1 |
Key Features
• Excellent Noise and Linearity up to and beyond FIN= 3 GHzConfigurable DDCDecimation Factors from 4 to 32 (Complex Baseband Out)Usable Output Bandwidth of 800 MHz at4x Decimation and 4000 MSPSUsable Output Bandwidth of 100 MHz at32x Decimation and 4000 MSPSBypass Mode for Full Nyquist Output BandwidthLow Pin-Count JESD204B Subclass 1 InterfaceAutomatically Optimized Output Lane CountEmbedded Low Latency Signal Range IndicationLow Power ConsumptionKey Specifications:Max Sampling Rate: 4000 MSPSMin Sampling Rate: 1000 MSPSDDC Output Word Size: 15-Bit Complex (30 bits total)Bypass Output Word Size: 12-Bit Offset BinaryNoise Floor: −149 dBFS/Hz or −150.8 dBm/HzIMD3: −64 dBc (FIN= 2140 MHz ± 30 MHz at −13 dBFS)FPBW (–3 dB): 3.2 GHzPeak NPR: 46 dBSupply Voltages: 1.9 V and 1.2 VPower ConsumptionBypass (4000 MSPS): 2 WDecimate by 10 (4000 MSPS): 2 WPower Down Mode: <50 mWExcellent Noise and Linearity up to and beyond FIN= 3 GHzConfigurable DDCDecimation Factors from 4 to 32 (Complex Baseband Out)Usable Output Bandwidth of 800 MHz at4x Decimation and 4000 MSPSUsable Output Bandwidth of 100 MHz at32x Decimation and 4000 MSPSBypass Mode for Full Nyquist Output BandwidthLow Pin-Count JESD204B Subclass 1 InterfaceAutomatically Optimized Output Lane CountEmbedded Low Latency Signal Range IndicationLow Power ConsumptionKey Specifications:Max Sampling Rate: 4000 MSPSMin Sampling Rate: 1000 MSPSDDC Output Word Size: 15-Bit Complex (30 bits total)Bypass Output Word Size: 12-Bit Offset BinaryNoise Floor: −149 dBFS/Hz or −150.8 dBm/HzIMD3: −64 dBc (FIN= 2140 MHz ± 30 MHz at −13 dBFS)FPBW (–3 dB): 3.2 GHzPeak NPR: 46 dBSupply Voltages: 1.9 V and 1.2 VPower ConsumptionBypass (4000 MSPS): 2 WDecimate by 10 (4000 MSPS): 2 WPower Down Mode: <50 mW
Description
AI
The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.
A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.
The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA≤ 85°C) ambient temperature range.
The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.
A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.
The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA≤ 85°C) ambient temperature range.