ADC12QJ1600 Series

Quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Catalog

Quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Part	Mounting Type	Configuration	Voltage - Supply, Analog (Range 2 Min)	Voltage - Supply, Analog (Range 2 Max)	Voltage - Supply, Analog (Range 1 Max)	Voltage - Supply, Analog (Range 1 Min)	Ratio - ADC	Ratio - S/H	Operating Temperature (Min)	Operating Temperature (Max)	Package Length	Package Name	Package Width	Voltage - Supply, Digital (Min)	Voltage - Supply, Digital (Max)	Input Type	Data Interface	Number of Bits	Package / Case	Number of A/D Converters	Architecture	Sampling Rate (Per Second)	Number of Inputs
Texas Instruments ADC12QJ1600AAV	Surface Mount	ADC	1.8 V	2 V	1.15 V	1.05 V	4	0	-40 °C	85 °C	10 mm	144-FCBGA	10 mm	1.05 V	1.15 V	Differential	JESD204B/C	12 bits	144-FBGA FCBGA	4 count	Pipelined SAR	1.6 GHz	4
Texas Instruments ADC12QJ1600AAVT	Surface Mount	ADC	1.8 V	2 V	1.15 V	1.05 V	4	0	-40 °C	85 °C	10 mm	144-FCBGA	10 mm	1.05 V	1.15 V	Differential	JESD204B/C	12 bits	144-FBGA FCBGA	4 count	Pipelined SAR	1.6 GHz	4

Catalog

Quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Description

ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.