TPS70175 Series

The TPS70175 is designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS70175 ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS70175 voltage regulator offers low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. This device has a fixed 5 V/2.5 V voltage option. Regulator 1 can support up to 500 mA and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 280 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (for example, an overload condition), VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS70175 features aRESET(SVS, POR, or Power-On Reset).RESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset pins (MR1andMR2). When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high impedance state after a 30-ms delay.RESETgoes to the logic low state when the VOUT2regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on until VIN1reaches 2.5 V. The TPS70175 is designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS70175 ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS70175 voltage regulator offers low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. This device has a fixed 5 V/2.5 V voltage option. Regulator 1 can support up to 500 mA and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 280 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (for example, an overload condition), VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS70175 features aRESET(SVS, POR, or Power-On Reset).RESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset pins (MR1andMR2). When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high impedance state after a 30-ms delay.RESETgoes to the logic low state when the VOUT2regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on until VIN1reaches 2.5 V.