SN74LVC1G00-EP Series

Enhanced product single 1-input, 1.65-V to 5.5-V NAND gate

Link to Manufacturer Page: https://www.ti.com/

Catalog

Enhanced product single 1-input, 1.65-V to 5.5-V NAND gate

Part	Mounting Type	Max Propagation Delay @ V, Max CL	Logic Type	Current - Quiescent (Max) [Max]	Number of Inputs	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Package / Case	Number of Circuits	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package
Texas Instruments V62/04732-02XE	Surface Mount	5 ns	NAND Gate	10 µA	2	0.8 V	0.7 V	5.5 V	1.65 V	32 mA	32 mA	1.7 V	2 V	5-TSSOP, SC-70-5, SOT-353	1	-55 °C	125 °C	SC-70-5
Texas Instruments SN74LVC1G00IDCKREP	Surface Mount	4 ns	NAND Gate	10 µA	2	0.8 V	0.7 V	5.5 V	1.65 V	32 mA	32 mA	1.7 V	2 V	5-TSSOP, SC-70-5, SOT-353	1	-40 °C	85 °C	SC-70-5
Texas Instruments SN74LVC1G00MDBVREP	Surface Mount	5 ns	NAND Gate	10 µA	2	0.8 V	0.7 V	5.5 V	1.65 V	32 mA	32 mA	1.7 V	2 V	SC-74A, SOT-753	1	-55 °C	125 °C	SOT-23-5
Texas Instruments SN74LVC1G00MDCKREP	Surface Mount	5 ns	NAND Gate	10 µA	2	0.8 V	0.7 V	5.5 V	1.65 V	32 mA	32 mA	1.7 V	2 V	5-TSSOP, SC-70-5, SOT-353	1	-55 °C	125 °C	SC-70-5

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)Supports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 3.8 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)Supports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 3.8 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.