74SSTVF16857 Series

14-bit registered buffer with SSTL_2 inputs and outputs

Catalog(1 parts)

Part	Supplier Device Package	Number of Bits▲▼	Mounting Type	Operating Temperature▲▼	Operating Temperature▲▼	Package / Case▲▼	Package / Case	Package / Case▲▼	Logic Type	Supply Voltage▲▼	Supply Voltage▲▼
Texas Instruments SN74SSTVF16857GR Registered Buffer with SSTL_2 Compatible I/O for DDR IC 48-TSSOP	48-TSSOP	14 ul	Surface Mount	70 °C	0 °C	0.006099999882280827 m	48-TFSOP	0.006095999851822853 m	Registered Buffer with SSTL_2 Compatible I/O for DDR	2.700000047683716 V	2.299999952316284 V

Key Features

• Member of the Texas Instruments Widebus™ FamilyOperates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200Pinout and Functionality Compatible With JEDEC Standard SSTV16857600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM ApplicationsOutput Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM LoadOutputs Meet SSTL_2 Class I SpecificationsSupports SSTL_2 Data InputsDifferential Clock (CLK and CLK\) InputsSupports LVCMOS Switching Levels on the RESET\ InputRESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs LowFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyOperates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200Pinout and Functionality Compatible With JEDEC Standard SSTV16857600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM ApplicationsOutput Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM LoadOutputs Meet SSTL_2 Class I SpecificationsSupports SSTL_2 Data InputsDifferential Clock (CLK and CLK\) InputsSupports LVCMOS Switching Levels on the RESET\ InputRESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs LowFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.

Description

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCCoperation. All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications. The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low. The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up. This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCCoperation. All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications. The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low. The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.