74LVT125 Series

4-ch, 2.7-V to 3.6-V buffers with bus-hold, TTL-compatible CMOS inputs and 3-state outputs

Catalog(9 parts)

Part	Voltage - Supply▲▼	Voltage - Supply▲▼	Number of Bits per Element▲▼	Number of Elements▲▼	Supplier Device Package	Operating Temperature▲▼	Operating Temperature▲▼	Package / Case	Package / Case▲▼	Package / Case▲▼	Logic Type	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Output Type	Mounting Type	Current - Output High, Low▲▼	Package / Case▲▼	Package / Case▲▼	Qualification	Grade	Package / Case▲▼
Texas Instruments SN74LVT125QPWREP Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul	14-TSSOP	-40 °C	125 °C	14-TSSOP	0.004394200164824724 m	0.004399999976158142 m	Buffer, Non-Inverting	0.03200000151991844 A	0.03200000151991844 A	3-State	Surface Mount
Texas Instruments SN74LVT125PWRG4 Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul	14-TSSOP	-40 °C	85 °C	14-TSSOP	0.004394200164824724 m	0.004399999976158142 m	Buffer, Non-Inverting			3-State	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments SN74LVT125PWG4 Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul	14-TSSOP	-40 °C	85 °C	14-TSSOP	0.004394200164824724 m	0.004399999976158142 m	Buffer, Non-Inverting			3-State	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments SN74LVT125DBR Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SSOP	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul	14-SSOP	-40 °C	85 °C	14-SSOP			Buffer, Non-Inverting			3-State	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A	0.005308600142598152 m	0.0052999998442828655 m
Texas Instruments SN74LVT125QPWRG4Q1 Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul	14-TSSOP	-40 °C	125 °C	14-TSSOP	0.004394200164824724 m	0.004399999976158142 m	Buffer, Non-Inverting	0.03200000151991844 A	0.03200000151991844 A	3-State	Surface Mount				AEC-Q100	Automotive
Texas Instruments SN74LVT125QDRQ1 Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul		-40 °C	125 °C	14-SOIC			Buffer, Non-Inverting	0.03200000151991844 A	0.03200000151991844 A	3-State	Surface Mount			0.003911599982529879 m	AEC-Q100	Automotive	0.003899999894201755 m
Texas Instruments SN74LVT125DR Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul		-40 °C	85 °C	14-SOIC			Buffer, Non-Inverting			3-State	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A		0.003911599982529879 m			0.003899999894201755 m
Texas Instruments SN74LVT125DG4 Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul		-40 °C	85 °C	14-SOIC			Buffer, Non-Inverting			3-State	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A		0.003911599982529879 m			0.003899999894201755 m
Texas Instruments SN74LVT125D Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC	2.700000047683716 V	3.5999999046325684 V	1 ul	4 ul		-40 °C	85 °C	14-SOIC			Buffer, Non-Inverting			3-State	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A		0.003911599982529879 m			0.003899999894201755 m

Key Features

• Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Supports Unregulated Battery Operation Down to 2.7 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationBus-Hold Data Inputs Eliminate the Need for External Pullup ResistorsLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Supports Unregulated Battery Operation Down to 2.7 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationBus-Hold Data Inputs Eliminate the Need for External Pullup ResistorsLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)

Description

This bus buffer is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This bus buffer is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.