CDC208 Series

5-V dual 1-to-4 clock driver

Catalog

5-V dual 1-to-4 clock driver

Part	Package Width	Package Name	Package Length	Mounting Type	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Operating Temperature (Min)	Operating Temperature (Max)	Type	Number of Circuits	Differential Output	Differential Input	Input Ratio	Output Ratio	Frequency - Max	Output	Input
Texas Instruments CDC208-7DW
Texas Instruments CDC208NSG4	5.3 mm	20-SO 20-SOIC	0.209 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL
Texas Instruments CDC208NSRG4	5.3 mm	20-SO 20-SOIC	0.209 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL
Texas Instruments CDC208NSR	5.3 mm	20-SO 20-SOIC	0.209 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL
Texas Instruments CDC208DWR	7.5 mm	20-SOIC	0.295 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL
Texas Instruments CDC208DWRG4	7.5 mm	20-SOIC	0.295 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL
Texas Instruments CDC208DW	7.5 mm	20-SOIC	0.295 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL
Texas Instruments CDC208DBR
Texas Instruments CDC208NS	5.3 mm	20-SO 20-SOIC	0.209 in	Surface Mount	5.5 V	4.5 V	-40 °C	85 °C	Fanout Buffer (Distribution)	2	No	No	1	4	60 MHz	CMOS	TTL

Catalog

5-V dual 1-to-4 clock driver

Description

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input. Skew parameters are specified for a reduced temperature and voltage range common to many applications. The CDC208 is characterized for operation from -40°C to 85°C. The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input. Skew parameters are specified for a reduced temperature and voltage range common to many applications. The CDC208 is characterized for operation from -40°C to 85°C.